1 --- a/usr/src/pkgdefs/SUNWixgbe/postinstall Sat Nov 07 09:32:37 2009 -0800
2 +++ b/usr/src/pkgdefs/SUNWixgbe/postinstall Sun Nov 08 15:49:56 2009 +0800
3 @@ -139,10 +139,12 @@
4 "pciex8086,10f1"
5 "pciex8086,10f4"
6 "pciex8086,10f7"
7 + "pciex8086,10f8"
8 "pciex8086,10f9"
9 "pciex8086,10fb"
10 "pciex8086,10fc"
11 "pciex8086,1507"
12 "pciex8086,1508"
13 + "pciex8086,150b"
14 "pciex8086,1514"' \
15 -b "$BASEDIR" ixgbe
1.1 --- a/usr/src/uts/common/io/ixgbe/ixgbe_82598.c Sat Nov 07 09:32:37 2009 -0800
1.2 +++ b/usr/src/uts/common/io/ixgbe/ixgbe_82598.c Sun Nov 08 15:49:56 2009 +0800
1.3 @@ -26,7 +26,7 @@
1.4 * Use is subject to license terms.
1.5 */
1.6
1.7 -/* IntelVersion: 1.144 v2-9-1-1_2009-6-10_NSW1 */
1.8 +/* IntelVersion: 1.155 scm_100309_002210 */
1.9
1.10 #include "ixgbe_type.h"
1.11 #include "ixgbe_api.h"
1.12 @@ -39,16 +39,17 @@
1.13 ixgbe_link_speed *speed, bool *autoneg);
1.14 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
1.15 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num);
1.16 -static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw);
1.17 +static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
1.18 + bool autoneg_wait_to_complete);
1.19 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
1.20 ixgbe_link_speed *speed, bool *link_up, bool link_up_wait_to_complete);
1.21 -static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
1.22 +static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
1.23 ixgbe_link_speed speed, bool autoneg,
1.24 bool autoneg_wait_to_complete);
1.25 -static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
1.26 -static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
1.27 +static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
1.28 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete);
1.29 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
1.30 +s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw);
1.31 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
1.32 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
1.33 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan,
1.34 @@ -61,6 +62,50 @@
1.35 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);
1.36 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw);
1.37 void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw);
1.38 +void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw);
1.39 +
1.40 +/*
1.41 + * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
1.42 + * @hw: pointer to the HW structure
1.43 + *
1.44 + * The defaults for 82598 should be in the range of 50us to 50ms,
1.45 + * however the hardware default for these parts is 500us to 1ms which is less
1.46 + * than the 10ms recommended by the pci-e spec. To address this we need to
1.47 + * increase the value to either 10ms to 250ms for capability version 1 config,
1.48 + * or 16ms to 55ms for version 2.
1.49 + */
1.50 +void
1.51 +ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
1.52 +{
1.53 + u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
1.54 + u16 pcie_devctl2;
1.55 +
1.56 + /* only take action if timeout value is defaulted to 0 */
1.57 + if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
1.58 + goto out;
1.59 +
1.60 + /*
1.61 + * if capababilities version is type 1 we can write the
1.62 + * timeout of 10ms to 250ms through the GCR register
1.63 + */
1.64 + if (!(gcr & IXGBE_GCR_CAP_VER2)) {
1.65 + gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
1.66 + goto out;
1.67 + }
1.68 +
1.69 + /*
1.70 + * for version 2 capabilities we need to write the config space
1.71 + * directly in order to set the completion timeout value for
1.72 + * 16ms to 55ms
1.73 + */
1.74 + pcie_devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
1.75 + pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
1.76 + IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
1.77 +out:
1.78 + /* disable completion timeout resend */
1.79 + gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
1.80 + IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
1.81 +}
1.82
1.83 /*
1.84 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
1.85 @@ -73,6 +118,8 @@
1.86 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
1.87 {
1.88 u32 msix_count = 18;
1.89 +
1.90 + DEBUGFUNC("ixgbe_get_pcie_msix_count_82598");
1.91
1.92 if (hw->mac.msix_vectors_from_pcie) {
1.93 msix_count = IXGBE_READ_PCIE_WORD(hw,
1.94 @@ -102,6 +149,8 @@
1.95 struct ixgbe_phy_info *phy = &hw->phy;
1.96 s32 ret_val;
1.97
1.98 + DEBUGFUNC("ixgbe_init_ops_82598");
1.99 +
1.100 ret_val = ixgbe_init_phy_ops_generic(hw);
1.101 ret_val = ixgbe_init_ops_generic(hw);
1.102
1.103 @@ -109,6 +158,7 @@
1.104 phy->ops.init = &ixgbe_init_phy_ops_82598;
1.105
1.106 /* MAC */
1.107 + mac->ops.start_hw = &ixgbe_start_hw_82598;
1.108 mac->ops.reset_hw = &ixgbe_reset_hw_82598;
1.109 mac->ops.get_media_type = &ixgbe_get_media_type_82598;
1.110 mac->ops.get_supported_physical_layer =
1.111 @@ -139,7 +189,6 @@
1.112 /* Link */
1.113 mac->ops.check_link = &ixgbe_check_mac_link_82598;
1.114 mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
1.115 - mac->ops.setup_link_speed = &ixgbe_setup_mac_link_speed_82598;
1.116 mac->ops.get_link_capabilities =
1.117 &ixgbe_get_link_capabilities_82598;
1.118
1.119 @@ -163,27 +212,28 @@
1.120 s32 ret_val = IXGBE_SUCCESS;
1.121 u16 list_offset, data_offset;
1.122
1.123 + DEBUGFUNC("ixgbe_init_phy_ops_82598");
1.124 +
1.125 /* Identify the PHY */
1.126 phy->ops.identify(hw);
1.127
1.128 /* Overwrite the link function pointers if copper PHY */
1.129 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
1.130 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
1.131 - mac->ops.setup_link_speed =
1.132 - &ixgbe_setup_copper_link_speed_82598;
1.133 mac->ops.get_link_capabilities =
1.134 &ixgbe_get_copper_link_capabilities_generic;
1.135 }
1.136
1.137 switch (hw->phy.type) {
1.138 case ixgbe_phy_tn:
1.139 + phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
1.140 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
1.141 phy->ops.get_firmware_version =
1.142 &ixgbe_get_phy_firmware_version_tnx;
1.143 break;
1.144 case ixgbe_phy_aq:
1.145 phy->ops.get_firmware_version =
1.146 - &ixgbe_get_phy_firmware_version_aq;
1.147 + &ixgbe_get_phy_firmware_version_generic;
1.148 break;
1.149 case ixgbe_phy_nl:
1.150 phy->ops.reset = &ixgbe_reset_phy_nl;
1.151 @@ -213,6 +263,29 @@
1.152 }
1.153
1.154 /*
1.155 + * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
1.156 + * @hw: pointer to hardware structure
1.157 + *
1.158 + * Starts the hardware using the generic start_hw function.
1.159 + * Then set pcie completion timeout
1.160 + */
1.161 +s32
1.162 +ixgbe_start_hw_82598(struct ixgbe_hw *hw)
1.163 +{
1.164 + s32 ret_val = IXGBE_SUCCESS;
1.165 +
1.166 + DEBUGFUNC("ixgbe_start_hw_82598");
1.167 +
1.168 + ret_val = ixgbe_start_hw_generic(hw);
1.169 +
1.170 + /* set the completion timeout for interface */
1.171 + if (ret_val == IXGBE_SUCCESS)
1.172 + ixgbe_set_pcie_completion_timeout(hw);
1.173 +
1.174 + return (ret_val);
1.175 +}
1.176 +
1.177 +/*
1.178 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
1.179 * @hw: pointer to hardware structure
1.180 * @speed: pointer to link speed
1.181 @@ -226,6 +299,8 @@
1.182 {
1.183 s32 status = IXGBE_SUCCESS;
1.184 u32 autoc = 0;
1.185 +
1.186 + DEBUGFUNC("ixgbe_get_link_capabilities_82598");
1.187
1.188 /*
1.189 * Determine link capabilities based on the stored value of AUTOC,
1.190 @@ -282,6 +357,8 @@
1.191 {
1.192 enum ixgbe_media_type media_type;
1.193
1.194 + DEBUGFUNC("ixgbe_get_media_type_82598");
1.195 +
1.196 /* Detect if there is a copper PHY attached. */
1.197 if (hw->phy.type == ixgbe_phy_cu_unknown ||
1.198 hw->phy.type == ixgbe_phy_tn ||
1.199 @@ -299,15 +376,18 @@
1.200 break;
1.201 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1.202 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1.203 - case IXGBE_DEV_ID_82598EB_CX4:
1.204 - case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
1.205 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1.206 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1.207 case IXGBE_DEV_ID_82598EB_XF_LR:
1.208 case IXGBE_DEV_ID_82598EB_SFP_LOM:
1.209 media_type = ixgbe_media_type_fiber;
1.210 break;
1.211 + case IXGBE_DEV_ID_82598EB_CX4:
1.212 + case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
1.213 + media_type = ixgbe_media_type_cx4;
1.214 + break;
1.215 case IXGBE_DEV_ID_82598AT:
1.216 + case IXGBE_DEV_ID_82598AT2:
1.217 media_type = ixgbe_media_type_copper;
1.218 break;
1.219 default:
1.220 @@ -389,7 +469,7 @@
1.221 break;
1.222 default:
1.223 DEBUGOUT("Flow control param set incorrectly\n");
1.224 - ret_val = -IXGBE_ERR_CONFIG;
1.225 + ret_val = IXGBE_ERR_CONFIG;
1.226 goto out;
1.227 }
1.228
1.229 @@ -427,19 +507,21 @@
1.230 }
1.231
1.232 /*
1.233 - * ixgbe_setup_mac_link_82598 - Configures MAC link settings
1.234 + * ixgbe_start_mac_link_82598 - Configures MAC link settings
1.235 * @hw: pointer to hardware structure
1.236 *
1.237 * Configures link settings based on values in the ixgbe_hw struct.
1.238 * Restarts the link. Performs autonegotiation if needed.
1.239 */
1.240 static s32
1.241 -ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
1.242 +ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, bool autoneg_wait_to_complete)
1.243 {
1.244 u32 autoc_reg;
1.245 u32 links_reg;
1.246 u32 i;
1.247 s32 status = IXGBE_SUCCESS;
1.248 +
1.249 + DEBUGFUNC("ixgbe_start_mac_link_82598");
1.250
1.251 /* Restart link */
1.252 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1.253 @@ -447,7 +529,7 @@
1.254 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
1.255
1.256 /* Only poll for autoneg to complete if specified to do so */
1.257 - if (hw->phy.autoneg_wait_to_complete) {
1.258 + if (autoneg_wait_to_complete) {
1.259 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
1.260 IXGBE_AUTOC_LMS_KX4_AN ||
1.261 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
1.262 @@ -488,6 +570,8 @@
1.263 u32 links_reg;
1.264 u32 i;
1.265 u16 link_reg, adapt_comp_reg;
1.266 +
1.267 + DEBUGFUNC("ixgbe_check_mac_link_82598");
1.268
1.269 /*
1.270 * SERDES PHY requires us to read link status from undocumented
1.271 @@ -561,7 +645,7 @@
1.272 }
1.273
1.274 /*
1.275 - * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
1.276 + * ixgbe_setup_mac_link_82598 - Set MAC link speed
1.277 * @hw: pointer to hardware structure
1.278 * @speed: new link speed
1.279 * @autoneg: true if autonegotiation enabled
1.280 @@ -570,7 +654,7 @@
1.281 * Set the link speed in the AUTOC register and restarts link.
1.282 */
1.283 static s32
1.284 -ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
1.285 +ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
1.286 ixgbe_link_speed speed, bool autoneg,
1.287 bool autoneg_wait_to_complete)
1.288 {
1.289 @@ -579,6 +663,8 @@
1.290 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1.291 u32 autoc = curr_autoc;
1.292 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
1.293 +
1.294 + DEBUGFUNC("ixgbe_setup_mac_link_82598");
1.295
1.296 /* Check to see if speed passed in is supported. */
1.297 (void) ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
1.298 @@ -599,45 +685,20 @@
1.299 }
1.300
1.301 if (status == IXGBE_SUCCESS) {
1.302 - hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
1.303 -
1.304 /*
1.305 * Setup and restart the link based on the new values in
1.306 * ixgbe_hw This will write the AUTOC register based on the new
1.307 * stored values
1.308 */
1.309 - status = ixgbe_setup_mac_link_82598(hw);
1.310 + status = ixgbe_start_mac_link_82598(hw,
1.311 + autoneg_wait_to_complete);
1.312 }
1.313
1.314 return (status);
1.315 }
1.316
1.317 -
1.318 /*
1.319 - * ixgbe_setup_copper_link_82598 - Setup copper link settings
1.320 - * @hw: pointer to hardware structure
1.321 - *
1.322 - * Configures link settings based on values in the ixgbe_hw struct.
1.323 - * Restarts the link. Performs autonegotiation if needed. Restart
1.324 - * phy and wait for autonegotiate to finish. Then synchronize the
1.325 - * MAC and PHY.
1.326 - */
1.327 -static s32
1.328 -ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
1.329 -{
1.330 - s32 status;
1.331 -
1.332 - /* Restart autonegotiation on PHY */
1.333 - status = hw->phy.ops.setup_link(hw);
1.334 -
1.335 - /* Set up MAC */
1.336 - (void) ixgbe_setup_mac_link_82598(hw);
1.337 -
1.338 - return (status);
1.339 -}
1.340 -
1.341 -/*
1.342 - * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
1.343 + * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
1.344 * @hw: pointer to hardware structure
1.345 * @speed: new link speed
1.346 * @autoneg: true if autonegotiation enabled
1.347 @@ -646,19 +707,21 @@
1.348 * Sets the link speed in the AUTOC register in the MAC and restarts link.
1.349 */
1.350 static s32
1.351 -ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
1.352 +ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
1.353 ixgbe_link_speed speed,
1.354 bool autoneg,
1.355 bool autoneg_wait_to_complete)
1.356 {
1.357 s32 status;
1.358
1.359 + DEBUGFUNC("ixgbe_setup_copper_link_82598");
1.360 +
1.361 /* Setup the PHY according to input speed */
1.362 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
1.363 autoneg_wait_to_complete);
1.364
1.365 /* Set up MAC */
1.366 - (void) ixgbe_setup_mac_link_82598(hw);
1.367 + (void) ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
1.368
1.369 return (status);
1.370 }
1.371 @@ -681,6 +744,8 @@
1.372 u32 i;
1.373 u32 autoc;
1.374 u8 analog_val;
1.375 +
1.376 + DEBUGFUNC("ixgbe_reset_hw_82598");
1.377
1.378 /* Call adapter stop to disable tx/rx and clear interrupts */
1.379 hw->mac.ops.stop_adapter(hw);
1.380 @@ -809,6 +874,8 @@
1.381 {
1.382 u32 rar_high;
1.383
1.384 + DEBUGFUNC("ixgbe_set_vmdq_82598");
1.385 +
1.386 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
1.387 rar_high &= ~IXGBE_RAH_VIND_MASK;
1.388 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
1.389 @@ -860,6 +927,8 @@
1.390 u32 bits;
1.391 u32 vftabyte;
1.392
1.393 + DEBUGFUNC("ixgbe_set_vfta_82598");
1.394 +
1.395 if (vlan > 4095)
1.396 return (IXGBE_ERR_PARAM);
1.397
1.398 @@ -903,6 +972,8 @@
1.399 u32 offset;
1.400 u32 vlanbyte;
1.401
1.402 + DEBUGFUNC("ixgbe_clear_vfta_82598");
1.403 +
1.404 for (offset = 0; offset < hw->mac.vft_size; offset++)
1.405 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1.406
1.407 @@ -927,6 +998,8 @@
1.408 {
1.409 u32 atlas_ctl;
1.410
1.411 + DEBUGFUNC("ixgbe_read_analog_reg8_82598");
1.412 +
1.413 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
1.414 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
1.415 IXGBE_WRITE_FLUSH(hw);
1.416 @@ -949,6 +1022,8 @@
1.417 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
1.418 {
1.419 u32 atlas_ctl;
1.420 +
1.421 + DEBUGFUNC("ixgbe_write_analog_reg8_82598");
1.422
1.423 atlas_ctl = (reg << 8) | val;
1.424 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1.425 @@ -975,6 +1050,8 @@
1.426 u16 sfp_data = 0;
1.427 u16 sfp_stat = 0;
1.428 u32 i;
1.429 +
1.430 + DEBUGFUNC("ixgbe_read_i2c_eeprom_82598");
1.431
1.432 if (hw->phy.type == ixgbe_phy_nl) {
1.433 /*
1.434 @@ -1032,6 +1109,8 @@
1.435 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1.436 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1.437 u16 ext_ability = 0;
1.438 +
1.439 + DEBUGFUNC("ixgbe_get_supported_physical_layer_82598");
1.440
1.441 hw->phy.ops.identify(hw);
1.442
1.443 @@ -1132,6 +1211,8 @@
1.444 struct ixgbe_bus_info *bus = &hw->bus;
1.445 u16 pci_gen, pci_ctrl2;
1.446
1.447 + DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie_82598");
1.448 +
1.449 ixgbe_set_lan_id_multi_port_pcie(hw);
1.450
1.451 /* check if LAN0 is disabled */
2.1 --- a/usr/src/uts/common/io/ixgbe/ixgbe_82599.c Sat Nov 07 09:32:37 2009 -0800
2.2 +++ b/usr/src/uts/common/io/ixgbe/ixgbe_82599.c Sun Nov 08 15:49:56 2009 +0800
2.3 @@ -26,42 +26,32 @@
2.4 * Use is subject to license terms.
2.5 */
2.6
2.7 -/* IntelVersion: 1.176 v2-9-1-1_2009-6-10_NSW1 */
2.8 +/* IntelVersion: 1.197 scm_100309_002210 */
2.9
2.10 #include "ixgbe_type.h"
2.11 #include "ixgbe_api.h"
2.12 #include "ixgbe_common.h"
2.13 #include "ixgbe_phy.h"
2.14
2.15 -u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw);
2.16 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);
2.17 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
2.18 ixgbe_link_speed *speed, bool *autoneg);
2.19 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
2.20 -s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw);
2.21 -s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
2.22 +s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
2.23 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete);
2.24 -s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw);
2.25 -s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
2.26 - ixgbe_link_speed *speed,
2.27 - bool *link_up, bool link_up_wait_to_complete);
2.28 -s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
2.29 +s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
2.30 + ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete);
2.31 +s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
2.32 + bool autoneg_wait_to_complete);
2.33 +s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
2.34 ixgbe_link_speed speed, bool autoneg,
2.35 bool autoneg_wait_to_complete);
2.36 -static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw);
2.37 -static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
2.38 +static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
2.39 ixgbe_link_speed speed, bool autoneg,
2.40 bool autoneg_wait_to_complete);
2.41 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw);
2.42 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw);
2.43 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
2.44 -s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
2.45 -s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
2.46 -s32 ixgbe_insert_mac_addr_82599(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
2.47 -s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan,
2.48 - u32 vind, bool vlan_on);
2.49 -s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw);
2.50 -s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw);
2.51 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
2.52 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
2.53 s32 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw);
2.54 @@ -69,10 +59,6 @@
2.55 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw);
2.56 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
2.57 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval);
2.58 -s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
2.59 - u16 *san_mac_offset);
2.60 -s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr);
2.61 -s32 ixgbe_set_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr);
2.62 s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps);
2.63 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
2.64
2.65 @@ -85,15 +71,14 @@
2.66
2.67 if (hw->phy.multispeed_fiber) {
2.68 /* Set up dual speed SFP+ support */
2.69 - mac->ops.setup_link =
2.70 - &ixgbe_setup_mac_link_multispeed_fiber;
2.71 - mac->ops.setup_link_speed =
2.72 - &ixgbe_setup_mac_link_speed_multispeed_fiber;
2.73 + mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
2.74 } else {
2.75 - mac->ops.setup_link =
2.76 - &ixgbe_setup_mac_link_82599;
2.77 - mac->ops.setup_link_speed =
2.78 - &ixgbe_setup_mac_link_speed_82599;
2.79 + if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
2.80 + (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
2.81 + hw->phy.smart_speed == ixgbe_smart_speed_on))
2.82 + mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
2.83 + else
2.84 + mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
2.85 }
2.86 }
2.87
2.88 @@ -128,8 +113,6 @@
2.89 /* If copper media, overwrite with copper function pointers */
2.90 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
2.91 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
2.92 - mac->ops.setup_link_speed =
2.93 - &ixgbe_setup_copper_link_speed_82599;
2.94 mac->ops.get_link_capabilities =
2.95 &ixgbe_get_copper_link_capabilities_generic;
2.96 }
2.97 @@ -143,7 +126,7 @@
2.98 break;
2.99 case ixgbe_phy_aq:
2.100 phy->ops.get_firmware_version =
2.101 - &ixgbe_get_phy_firmware_version_aq;
2.102 + &ixgbe_get_phy_firmware_version_generic;
2.103 break;
2.104 default:
2.105 break;
2.106 @@ -200,33 +183,6 @@
2.107 }
2.108
2.109 /*
2.110 - * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
2.111 - * @hw: pointer to hardware structure
2.112 - *
2.113 - * Read PCIe configuration space, and get the MSI-X vector count from
2.114 - * the capabilities table.
2.115 - */
2.116 -u32
2.117 -ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
2.118 -{
2.119 - u32 msix_count = 64;
2.120 -
2.121 - if (hw->mac.msix_vectors_from_pcie) {
2.122 - msix_count = IXGBE_READ_PCIE_WORD(hw,
2.123 - IXGBE_PCIE_MSIX_82599_CAPS);
2.124 - msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2.125 -
2.126 - /*
2.127 - * MSI-X count is zero-based in HW, so increment to give
2.128 - * proper value
2.129 - */
2.130 - msix_count++;
2.131 - }
2.132 -
2.133 - return (msix_count);
2.134 -}
2.135 -
2.136 -/*
2.137 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
2.138 * @hw: pointer to hardware structure
2.139 *
2.140 @@ -240,6 +196,8 @@
2.141 struct ixgbe_mac_info *mac = &hw->mac;
2.142 struct ixgbe_phy_info *phy = &hw->phy;
2.143 s32 ret_val;
2.144 +
2.145 + DEBUGFUNC("ixgbe_init_ops_82599");
2.146
2.147 ret_val = ixgbe_init_phy_ops_generic(hw);
2.148 ret_val = ixgbe_init_ops_generic(hw);
2.149 @@ -257,23 +215,24 @@
2.150 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
2.151 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
2.152 mac->ops.start_hw = &ixgbe_start_hw_rev_1_82599;
2.153 - mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_82599;
2.154 - mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_82599;
2.155 + mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
2.156 + mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
2.157 mac->ops.get_device_caps = &ixgbe_get_device_caps_82599;
2.158 + mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
2.159
2.160 /* RAR, Multicast, VLAN */
2.161 - mac->ops.set_vmdq = &ixgbe_set_vmdq_82599;
2.162 - mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82599;
2.163 - mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_82599;
2.164 + mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
2.165 + mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
2.166 + mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
2.167 mac->rar_highwater = 1;
2.168 - mac->ops.set_vfta = &ixgbe_set_vfta_82599;
2.169 - mac->ops.clear_vfta = &ixgbe_clear_vfta_82599;
2.170 - mac->ops.init_uta_tables = &ixgbe_init_uta_tables_82599;
2.171 + mac->ops.set_vfta = &ixgbe_set_vfta_generic;
2.172 + mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
2.173 + mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
2.174 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
2.175
2.176 /* Link */
2.177 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
2.178 - mac->ops.check_link = &ixgbe_check_mac_link_82599;
2.179 + mac->ops.check_link = &ixgbe_check_mac_link_generic;
2.180 ixgbe_init_mac_link_ops_82599(hw);
2.181
2.182 mac->mcft_size = 128;
2.183 @@ -281,7 +240,7 @@
2.184 mac->num_rar_entries = 128;
2.185 mac->max_tx_queues = 128;
2.186 mac->max_rx_queues = 128;
2.187 - mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
2.188 + mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
2.189
2.190 return (ret_val);
2.191 }
2.192 @@ -300,6 +259,8 @@
2.193 {
2.194 s32 status = IXGBE_SUCCESS;
2.195 u32 autoc = 0;
2.196 +
2.197 + DEBUGFUNC("ixgbe_get_link_capabilities_82599");
2.198
2.199 /*
2.200 * Determine link capabilities based on the stored value of AUTOC,
2.201 @@ -386,6 +347,8 @@
2.202 {
2.203 enum ixgbe_media_type media_type;
2.204
2.205 + DEBUGFUNC("ixgbe_get_media_type_82599");
2.206 +
2.207 /* Detect if there is a copper PHY attached. */
2.208 if (hw->phy.type == ixgbe_phy_cu_unknown ||
2.209 hw->phy.type == ixgbe_phy_tn ||
2.210 @@ -396,17 +359,18 @@
2.211
2.212 switch (hw->device_id) {
2.213 case IXGBE_DEV_ID_82599_KX4:
2.214 - case IXGBE_DEV_ID_82599_KX4_SIK:
2.215 + case IXGBE_DEV_ID_82599_KX4_MEZZ:
2.216 + case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
2.217 case IXGBE_DEV_ID_82599_XAUI_LOM:
2.218 /* Default device ID is mezzanine card KX/KX4 */
2.219 media_type = ixgbe_media_type_backplane;
2.220 break;
2.221 case IXGBE_DEV_ID_82599_SFP:
2.222 - case IXGBE_DEV_ID_82599_SPW:
2.223 + case IXGBE_DEV_ID_82599_SFP_EM:
2.224 media_type = ixgbe_media_type_fiber;
2.225 break;
2.226 case IXGBE_DEV_ID_82599_CX4:
2.227 - media_type = ixgbe_media_type_fiber;
2.228 + media_type = ixgbe_media_type_cx4;
2.229 break;
2.230 default:
2.231 media_type = ixgbe_media_type_unknown;
2.232 @@ -417,19 +381,21 @@
2.233 }
2.234
2.235 /*
2.236 - * ixgbe_setup_mac_link_82599 - Setup MAC link settings
2.237 + * ixgbe_start_mac_link_82599 - Setup MAC link settings
2.238 * @hw: pointer to hardware structure
2.239 *
2.240 * Configures link settings based on values in the ixgbe_hw struct.
2.241 * Restarts the link. Performs autonegotiation if needed.
2.242 */
2.243 s32
2.244 -ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw)
2.245 +ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, bool autoneg_wait_to_complete)
2.246 {
2.247 u32 autoc_reg;
2.248 u32 links_reg;
2.249 u32 i;
2.250 s32 status = IXGBE_SUCCESS;
2.251 +
2.252 + DEBUGFUNC("ixgbe_start_mac_link_82599");
2.253
2.254 /* Restart link */
2.255 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2.256 @@ -437,7 +403,7 @@
2.257 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2.258
2.259 /* Only poll for autoneg to complete if specified to do so */
2.260 - if (hw->phy.autoneg_wait_to_complete) {
2.261 + if (autoneg_wait_to_complete) {
2.262 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
2.263 IXGBE_AUTOC_LMS_KX4_KX_KR ||
2.264 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
2.265 @@ -465,28 +431,7 @@
2.266 }
2.267
2.268 /*
2.269 - * ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings
2.270 - * @hw: pointer to hardware structure
2.271 - *
2.272 - * Configures link settings based on values in the ixgbe_hw struct.
2.273 - * Restarts the link for multi-speed fiber at 1G speed, if link
2.274 - * fails at 10G.
2.275 - * Performs autonegotiation if needed.
2.276 - */
2.277 -s32
2.278 -ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw)
2.279 -{
2.280 - s32 status = IXGBE_SUCCESS;
2.281 - ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2.282 - DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
2.283 -
2.284 - status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw,
2.285 - link_speed, true, true);
2.286 - return (status);
2.287 -}
2.288 -
2.289 -/*
2.290 - * ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed
2.291 + * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
2.292 * @hw: pointer to hardware structure
2.293 * @speed: new link speed
2.294 * @autoneg: true if autonegotiation enabled
2.295 @@ -495,7 +440,7 @@
2.296 * Set the link speed in the AUTOC register and restarts link.
2.297 */
2.298 s32
2.299 -ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
2.300 +ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
2.301 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete)
2.302 {
2.303 s32 status = IXGBE_SUCCESS;
2.304 @@ -507,21 +452,14 @@
2.305 bool link_up = false;
2.306 bool negotiation;
2.307
2.308 + DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
2.309 +
2.310 /* Mask off requested but non-supported speeds */
2.311 status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation);
2.312 if (status != IXGBE_SUCCESS)
2.313 - goto out;
2.314 + return (status);
2.315
2.316 speed &= link_speed;
2.317 -
2.318 - /* Set autoneg_advertised value based on input link speed */
2.319 - hw->phy.autoneg_advertised = 0;
2.320 -
2.321 - if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2.322 - hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
2.323 -
2.324 - if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2.325 - hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
2.326
2.327 /*
2.328 * When the driver changes the link speeds that it can support,
2.329 @@ -544,7 +482,7 @@
2.330 /* If we already have link at this speed, just jump out */
2.331 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
2.332 if (status != IXGBE_SUCCESS)
2.333 - goto out;
2.334 + return (status);
2.335
2.336 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
2.337 goto out;
2.338 @@ -556,11 +494,11 @@
2.339 /* Allow module to change analog characteristics (1G->10G) */
2.340 msec_delay(40);
2.341
2.342 - status = ixgbe_setup_mac_link_speed_82599(
2.343 + status = ixgbe_setup_mac_link_82599(
2.344 hw, IXGBE_LINK_SPEED_10GB_FULL, autoneg,
2.345 autoneg_wait_to_complete);
2.346 if (status != IXGBE_SUCCESS)
2.347 - goto out;
2.348 + return (status);
2.349
2.350 /* Flap the tx laser if it has not already been done */
2.351 if (hw->mac.autotry_restart) {
2.352 @@ -577,7 +515,11 @@
2.353 hw->mac.autotry_restart = false;
2.354 }
2.355
2.356 - /* The controller may take up to 500ms at 10g to acquire link */
2.357 + /*
2.358 + * Wait for the controller to acquire link. Per IEEE 802.3ap,
2.359 + * Section 73.10.2, we may have to wait up to 500ms if KR is
2.360 + * attempted. 82599 uses the same timing for 10g SFI.
2.361 + */
2.362 for (i = 0; i < 5; i++) {
2.363 /* Wait for the link partner to also set speed */
2.364 msec_delay(100);
2.365 @@ -586,7 +528,7 @@
2.366 status = ixgbe_check_link(hw, &link_speed,
2.367 &link_up, false);
2.368 if (status != IXGBE_SUCCESS)
2.369 - goto out;
2.370 + return (status);
2.371
2.372 if (link_up)
2.373 goto out;
2.374 @@ -601,7 +543,7 @@
2.375 /* If we already have link at this speed, just jump out */
2.376 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
2.377 if (status != IXGBE_SUCCESS)
2.378 - goto out;
2.379 + return (status);
2.380
2.381 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
2.382 goto out;
2.383 @@ -614,11 +556,11 @@
2.384 /* Allow module to change analog characteristics (10G->1G) */
2.385 msec_delay(40);
2.386
2.387 - status = ixgbe_setup_mac_link_speed_82599(
2.388 + status = ixgbe_setup_mac_link_82599(
2.389 hw, IXGBE_LINK_SPEED_1GB_FULL, autoneg,
2.390 autoneg_wait_to_complete);
2.391 if (status != IXGBE_SUCCESS)
2.392 - goto out;
2.393 + return (status);
2.394
2.395 /* Flap the tx laser if it has not already been done */
2.396 if (hw->mac.autotry_restart) {
2.397 @@ -641,7 +583,7 @@
2.398 /* If we have link, just jump out */
2.399 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
2.400 if (status != IXGBE_SUCCESS)
2.401 - goto out;
2.402 + return (status);
2.403
2.404 if (link_up)
2.405 goto out;
2.406 @@ -653,68 +595,134 @@
2.407 * single highest speed that the user requested.
2.408 */
2.409 if (speedcnt > 1)
2.410 - status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw,
2.411 + status = ixgbe_setup_mac_link_multispeed_fiber(hw,
2.412 highest_link_speed, autoneg, autoneg_wait_to_complete);
2.413 +
2.414 +out:
2.415 + /* Set autoneg_advertised value based on input link speed */
2.416 + hw->phy.autoneg_advertised = 0;
2.417 +
2.418 + if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2.419 + hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
2.420 +
2.421 + if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2.422 + hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
2.423 +
2.424 + return (status);
2.425 +}
2.426 +
2.427 +/*
2.428 + * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
2.429 + * @hw: pointer to hardware structure
2.430 + * @speed: new link speed
2.431 + * @autoneg: true if autonegotiation enabled
2.432 + * @autoneg_wait_to_complete: true when waiting for completion is needed
2.433 + *
2.434 + * Implements the Intel SmartSpeed algorithm.
2.435 + */
2.436 +s32
2.437 +ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
2.438 + ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete)
2.439 +{
2.440 + s32 status = IXGBE_SUCCESS;
2.441 + ixgbe_link_speed link_speed;
2.442 + s32 i, j;
2.443 + bool link_up = false;
2.444 + u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2.445 +
2.446 + DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
2.447 +
2.448 + /* Set autoneg_advertised value based on input link speed */
2.449 + hw->phy.autoneg_advertised = 0;
2.450 +
2.451 + if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2.452 + hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
2.453 +
2.454 + if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2.455 + hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
2.456 +
2.457 + if (speed & IXGBE_LINK_SPEED_100_FULL)
2.458 + hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
2.459 +
2.460 + /*
2.461 + * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
2.462 + * autoneg advertisement if link is unable to be established at the
2.463 + * highest negotiated rate. This can sometimes happen due to integrity
2.464 + * issues with the physical media connection.
2.465 + */
2.466 +
2.467 + /* First, try to get link with full advertisement */
2.468 + hw->phy.smart_speed_active = false;
2.469 + for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
2.470 + status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
2.471 + autoneg_wait_to_complete);
2.472 + if (status != IXGBE_SUCCESS)
2.473 + goto out;
2.474 +
2.475 + /*
2.476 + * Wait for the controller to acquire link. Per IEEE 802.3ap,
2.477 + * Section 73.10.2, we may have to wait up to 500ms if KR is
2.478 + * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
2.479 + * Table 9 in the AN MAS.
2.480 + */
2.481 + for (i = 0; i < 5; i++) {
2.482 + msec_delay(100);
2.483 +
2.484 + /* If we have link, just jump out */
2.485 + status = ixgbe_check_link(hw, &link_speed, &link_up,
2.486 + false);
2.487 + if (status != IXGBE_SUCCESS)
2.488 + goto out;
2.489 +
2.490 + if (link_up)
2.491 + goto out;
2.492 + }
2.493 + }
2.494 +
2.495 + /*
2.496 + * We didn't get link. If we advertised KR plus one of KX4/KX
2.497 + * (or BX4/BX), then disable KR and try again.
2.498 + */
2.499 + if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
2.500 + ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
2.501 + goto out;
2.502 +
2.503 + /* Turn SmartSpeed on to disable KR support */
2.504 + hw->phy.smart_speed_active = true;
2.505 + status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
2.506 + autoneg_wait_to_complete);
2.507 + if (status != IXGBE_SUCCESS)
2.508 + goto out;
2.509 +
2.510 + /*
2.511 + * Wait for the controller to acquire link. 600ms will allow for
2.512 + * the AN link_fail_inhibit_timer as well for multiple cycles of
2.513 + * parallel detect, both 10g and 1g. This allows for the maximum
2.514 + * connect attempts as defined in the AN MAS table 73-7.
2.515 + */
2.516 + for (i = 0; i < 6; i++) {
2.517 + msec_delay(100);
2.518 +
2.519 + /* If we have link, just jump out */
2.520 + status = ixgbe_check_link(hw, &link_speed, &link_up, false);
2.521 + if (status != IXGBE_SUCCESS)
2.522 + goto out;
2.523 +
2.524 + if (link_up)
2.525 + goto out;
2.526 + }
2.527 +
2.528 + /* We didn't get link. Turn SmartSpeed back off. */
2.529 + hw->phy.smart_speed_active = false;
2.530 + status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
2.531 + autoneg_wait_to_complete);
2.532
2.533 out:
2.534 return (status);
2.535 }
2.536
2.537 /*
2.538 - * ixgbe_check_mac_link_82599 - Determine link and speed status
2.539 - * @hw: pointer to hardware structure
2.540 - * @speed: pointer to link speed
2.541 - * @link_up: true when link is up
2.542 - * @link_up_wait_to_complete: bool used to wait for link up or not
2.543 - *
2.544 - * Reads the links register to determine if link is up and the current speed
2.545 - */
2.546 -s32
2.547 -ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2.548 - bool *link_up, bool link_up_wait_to_complete)
2.549 -{
2.550 - u32 links_reg;
2.551 - u32 i;
2.552 -
2.553 - links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
2.554 - if (link_up_wait_to_complete) {
2.555 - for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
2.556 - if (links_reg & IXGBE_LINKS_UP) {
2.557 - *link_up = true;
2.558 - break;
2.559 - } else {
2.560 - *link_up = false;
2.561 - }
2.562 - msec_delay(100);
2.563 - links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
2.564 - }
2.565 - } else {
2.566 - if (links_reg & IXGBE_LINKS_UP)
2.567 - *link_up = true;
2.568 - else
2.569 - *link_up = false;
2.570 - }
2.571 -
2.572 - if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2.573 - IXGBE_LINKS_SPEED_10G_82599)
2.574 - *speed = IXGBE_LINK_SPEED_10GB_FULL;
2.575 - else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2.576 - IXGBE_LINKS_SPEED_1G_82599)
2.577 - *speed = IXGBE_LINK_SPEED_1GB_FULL;
2.578 - else
2.579 - *speed = IXGBE_LINK_SPEED_100_FULL;
2.580 -
2.581 - /* if link is down, zero out the current_mode */
2.582 - if (*link_up == false) {
2.583 - hw->fc.current_mode = ixgbe_fc_none;
2.584 - hw->fc.fc_was_autonegged = false;
2.585 - }
2.586 -
2.587 - return (IXGBE_SUCCESS);
2.588 -}
2.589 -
2.590 -/*
2.591 - * ixgbe_setup_mac_link_speed_82599 - Set MAC link speed
2.592 + * ixgbe_setup_mac_link_82599 - Set MAC link speed
2.593 * @hw: pointer to hardware structure
2.594 * @speed: new link speed
2.595 * @autoneg: true if autonegotiation enabled
2.596 @@ -723,7 +731,7 @@
2.597 * Set the link speed in the AUTOC register and restarts link.
2.598 */
2.599 s32
2.600 -ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
2.601 +ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
2.602 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete)
2.603 {
2.604 s32 status = IXGBE_SUCCESS;
2.605 @@ -737,6 +745,8 @@
2.606 u32 links_reg;
2.607 u32 i;
2.608 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
2.609 +
2.610 + DEBUGFUNC("ixgbe_setup_mac_link_82599");
2.611
2.612 /* Check to see if speed passed in is supported. */
2.613 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
2.614 @@ -766,7 +776,8 @@
2.615 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2.616 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
2.617 autoc |= IXGBE_AUTOC_KX4_SUPP;
2.618 - if (orig_autoc & IXGBE_AUTOC_KR_SUPP)
2.619 + if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
2.620 + (hw->phy.smart_speed_active == false))
2.621 autoc |= IXGBE_AUTOC_KR_SUPP;
2.622 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2.623 autoc |= IXGBE_AUTOC_KX_SUPP;
2.624 @@ -827,27 +838,7 @@
2.625 }
2.626
2.627 /*
2.628 - * ixgbe_setup_copper_link_82599 - Setup copper link settings
2.629 - * @hw: pointer to hardware structure
2.630 - *
2.631 - * Restarts the link on PHY and then MAC. Performs autonegotiation if needed.
2.632 - */
2.633 -static s32
2.634 -ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw)
2.635 -{
2.636 - s32 status;
2.637 -
2.638 - /* Restart autonegotiation on PHY */
2.639 - status = hw->phy.ops.setup_link(hw);
2.640 -
2.641 - /* Set up MAC */
2.642 - (void) ixgbe_setup_mac_link_82599(hw);
2.643 -
2.644 - return (status);
2.645 -}
2.646 -
2.647 -/*
2.648 - * ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field
2.649 + * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
2.650 * @hw: pointer to hardware structure
2.651 * @speed: new link speed
2.652 * @autoneg: true if autonegotiation enabled
2.653 @@ -856,16 +847,18 @@
2.654 * Restarts link on PHY and MAC based on settings passed in.
2.655 */
2.656 static s32
2.657 -ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
2.658 +ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
2.659 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete)
2.660 {
2.661 s32 status;
2.662 +
2.663 + DEBUGFUNC("ixgbe_setup_copper_link_82599");
2.664
2.665 /* Setup the PHY according to input speed */
2.666 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
2.667 autoneg_wait_to_complete);
2.668 /* Set up MAC */
2.669 - (void) ixgbe_setup_mac_link_82599(hw);
2.670 + (void) ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
2.671
2.672 return (status);
2.673 }
2.674 @@ -885,6 +878,8 @@
2.675 u32 i;
2.676 u32 autoc;
2.677 u32 autoc2;
2.678 +
2.679 + DEBUGFUNC("ixgbe_reset_hw_82599");
2.680
2.681 /* Call adapter stop to disable tx/rx and clear interrupts */
2.682 hw->mac.ops.stop_adapter(hw);
2.683 @@ -997,316 +992,12 @@
2.684 hw->mac.num_rar_entries--;
2.685 }
2.686
2.687 + /* Store the alternative WWNN/WWPN prefix */
2.688 + hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
2.689 + &hw->mac.wwpn_prefix);
2.690 +
2.691 reset_hw_out:
2.692 return (status);
2.693 -}
2.694 -
2.695 -/*
2.696 - * ixgbe_insert_mac_addr_82599 - Find a RAR for this mac address
2.697 - * @hw: pointer to hardware structure
2.698 - * @addr: Address to put into receive address register
2.699 - * @vmdq: VMDq pool to assign
2.700 - *
2.701 - * Puts an ethernet address into a receive address register, or
2.702 - * finds the rar that it is aleady in; adds to the pool list
2.703 - */
2.704 -s32
2.705 -ixgbe_insert_mac_addr_82599(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2.706 -{
2.707 - static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
2.708 - u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
2.709 - u32 rar;
2.710 - u32 rar_low, rar_high;
2.711 - u32 addr_low, addr_high;
2.712 -
2.713 - /* swap bytes for HW little endian */
2.714 - addr_low = addr[0] | (addr[1] << 8)
2.715 - | (addr[2] << 16)
2.716 - | (addr[3] << 24);
2.717 - addr_high = addr[4] | (addr[5] << 8);
2.718 -
2.719 - /*
2.720 - * Either find the mac_id in rar or find the first empty space.
2.721 - * rar_highwater points to just after the highest currently used
2.722 - * rar in order to shorten the search. It grows when we add a new
2.723 - * rar to the top.
2.724 - */
2.725 - for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
2.726 - rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
2.727 -
2.728 - if (((IXGBE_RAH_AV & rar_high) == 0) &&
2.729 - first_empty_rar == NO_EMPTY_RAR_FOUND) {
2.730 - first_empty_rar = rar;
2.731 - } else if ((rar_high & 0xFFFF) == addr_high) {
2.732 - rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
2.733 - if (rar_low == addr_low)
2.734 - break; /* found it already in the rars */
2.735 - }
2.736 - }
2.737 -
2.738 - if (rar < hw->mac.rar_highwater) {
2.739 - /* already there so just add to the pool bits */
2.740 - (void) ixgbe_set_vmdq(hw, rar, vmdq);
2.741 - } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
2.742 - /* stick it into first empty RAR slot we found */
2.743 - rar = first_empty_rar;
2.744 - (void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2.745 - } else if (rar == hw->mac.rar_highwater) {
2.746 - /* add it to the top of the list and inc the highwater mark */
2.747 - (void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2.748 - hw->mac.rar_highwater++;
2.749 - } else if (rar >= hw->mac.num_rar_entries) {
2.750 - return (IXGBE_ERR_INVALID_MAC_ADDR);
2.751 - }
2.752 -
2.753 - /*
2.754 - * If we found rar[0], make sure the default pool bit (we use pool 0)
2.755 - * remains cleared to be sure default pool packets will get delivered
2.756 - */
2.757 - if (rar == 0)
2.758 - (void) ixgbe_clear_vmdq(hw, rar, 0);
2.759 -
2.760 - return (rar);
2.761 -}
2.762 -
2.763 -/*
2.764 - * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
2.765 - * @hw: pointer to hardware struct
2.766 - * @rar: receive address register index to disassociate
2.767 - * @vmdq: VMDq pool index to remove from the rar
2.768 - */
2.769 -s32
2.770 -ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2.771 -{
2.772 - u32 mpsar_lo, mpsar_hi;
2.773 - u32 rar_entries = hw->mac.num_rar_entries;
2.774 -
2.775 - if (rar < rar_entries) {
2.776 - mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2.777 - mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2.778 -
2.779 - if (!mpsar_lo && !mpsar_hi) {
2.780 - goto done;
2.781 - }
2.782 -
2.783 - if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2.784 - if (mpsar_lo) {
2.785 - IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2.786 - mpsar_lo = 0;
2.787 - }
2.788 - if (mpsar_hi) {
2.789 - IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2.790 - mpsar_hi = 0;
2.791 - }
2.792 - } else if (vmdq < 32) {
2.793 - mpsar_lo &= ~(1 << vmdq);
2.794 - IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
2.795 - } else {
2.796 - mpsar_hi &= ~(1 << (vmdq - 32));
2.797 - IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
2.798 - }
2.799 -
2.800 - /* was that the last pool using this rar? */
2.801 - if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) {
2.802 - hw->mac.ops.clear_rar(hw, rar);
2.803 - }
2.804 - } else {
2.805 - DEBUGOUT1("RAR index %d is out of range.\n", rar);
2.806 - return (IXGBE_ERR_PARAM);
2.807 - }
2.808 -done:
2.809 - return (IXGBE_SUCCESS);
2.810 -}
2.811 -
2.812 -/*
2.813 - * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
2.814 - * @hw: pointer to hardware struct
2.815 - * @rar: receive address register index to associate with a VMDq index
2.816 - * @vmdq: VMDq pool index
2.817 - */
2.818 -s32
2.819 -ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2.820 -{
2.821 - u32 mpsar;
2.822 - u32 rar_entries = hw->mac.num_rar_entries;
2.823 -
2.824 - if (rar < rar_entries) {
2.825 - if (vmdq < 32) {
2.826 - mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2.827 - mpsar |= 1 << vmdq;
2.828 - IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2.829 - } else {
2.830 - mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2.831 - mpsar |= 1 << (vmdq - 32);
2.832 - IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
2.833 - }
2.834 - } else {
2.835 - DEBUGOUT1("RAR index %d is out of range.\n", rar);
2.836 - return (IXGBE_ERR_PARAM);
2.837 - }
2.838 -
2.839 - return (IXGBE_SUCCESS);
2.840 -}
2.841 -
2.842 -/*
2.843 - * ixgbe_set_vfta_82599 - Set VLAN filter table
2.844 - * @hw: pointer to hardware structure
2.845 - * @vlan: VLAN id to write to VLAN filter
2.846 - * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2.847 - * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2.848 - *
2.849 - * Turn on/off specified VLAN in the VLAN filter table.
2.850 - */
2.851 -s32
2.852 -ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
2.853 -{
2.854 - u32 regindex;
2.855 - u32 bitindex;
2.856 - u32 bits;
2.857 - u32 first_empty_slot;
2.858 -
2.859 - if (vlan > 4095) {
2.860 - return (IXGBE_ERR_PARAM);
2.861 - }
2.862 -
2.863 - /*
2.864 - * this is a 2 part operation - first the VFTA, then the
2.865 - * VLVF and VLVFB if vind is set
2.866 - */
2.867 -
2.868 - /*
2.869 - * Part 1
2.870 - * The VFTA is a bitstring made up of 128 32-bit registers
2.871 - * that enable the particular VLAN id, much like the MTA:
2.872 - * bits[11-5]: which register
2.873 - * bits[4-0]: which bit in the register
2.874 - */
2.875 - regindex = (vlan >> 5) & 0x7F;
2.876 - bitindex = vlan & 0x1F;
2.877 - bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
2.878 - if (vlan_on) {
2.879 - bits |= (1 << bitindex);
2.880 - } else {
2.881 - bits &= ~(1 << bitindex);
2.882 - }
2.883 - IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
2.884 -
2.885 -
2.886 - /*
2.887 - * Part 2
2.888 - * If the vind is set
2.889 - * Either vlan_on
2.890 - * make sure the vlan is in VLVF
2.891 - * set the vind bit in the matching VLVFB
2.892 - * Or !vlan_on
2.893 - * clear the pool bit and possibly the vind
2.894 - */
2.895 - if (vind) {
2.896 - /* find the vlanid or the first empty slot */
2.897 - first_empty_slot = 0;
2.898 -
2.899 - for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2.900 - bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2.901 - if (!bits && !first_empty_slot)
2.902 - first_empty_slot = regindex;
2.903 - else if ((bits & 0x0FFF) == vlan)
2.904 - break;
2.905 - }
2.906 -
2.907 - if (regindex >= IXGBE_VLVF_ENTRIES) {
2.908 - if (first_empty_slot)
2.909 - regindex = first_empty_slot;
2.910 - else {
2.911 - DEBUGOUT("No space in VLVF.\n");
2.912 - goto out;
2.913 - }
2.914 - }
2.915 -
2.916 -
2.917 - if (vlan_on) {
2.918 - /* set the pool bit */
2.919 - if (vind < 32) {
2.920 - bits =
2.921 - IXGBE_READ_REG(hw, IXGBE_VLVFB(regindex*2));
2.922 - bits |= (1 << vind);
2.923 - IXGBE_WRITE_REG(hw,
2.924 - IXGBE_VLVFB(regindex*2), bits);
2.925 - } else {
2.926 - bits = IXGBE_READ_REG(hw,
2.927 - IXGBE_VLVFB((regindex*2)+1));
2.928 - bits |= (1 << vind);
2.929 - IXGBE_WRITE_REG(hw,
2.930 - IXGBE_VLVFB((regindex*2)+1), bits);
2.931 - }
2.932 - } else {
2.933 - /* clear the pool bit */
2.934 - if (vind < 32) {
2.935 - bits = IXGBE_READ_REG(hw,
2.936 - IXGBE_VLVFB(regindex*2));
2.937 - bits &= ~(1 << vind);
2.938 - IXGBE_WRITE_REG(hw,
2.939 - IXGBE_VLVFB(regindex*2), bits);
2.940 - bits |= IXGBE_READ_REG(hw,
2.941 - IXGBE_VLVFB((regindex*2)+1));
2.942 - } else {
2.943 - bits = IXGBE_READ_REG(hw,
2.944 - IXGBE_VLVFB((regindex*2)+1));
2.945 - bits &= ~(1 << vind);
2.946 - IXGBE_WRITE_REG(hw,
2.947 - IXGBE_VLVFB((regindex*2)+1), bits);
2.948 - bits |= IXGBE_READ_REG(hw,
2.949 - IXGBE_VLVFB(regindex*2));
2.950 - }
2.951 - }
2.952 -
2.953 - if (bits)
2.954 - IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
2.955 - (IXGBE_VLVF_VIEN | vlan));
2.956 - else
2.957 - IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
2.958 - }
2.959 -
2.960 -out:
2.961 - return (IXGBE_SUCCESS);
2.962 -}
2.963 -
2.964 -/*
2.965 - * ixgbe_clear_vfta_82599 - Clear VLAN filter table
2.966 - * @hw: pointer to hardware structure
2.967 - *
2.968 - * Clears the VLAN filer table, and the VMDq index associated with the filter
2.969 - */
2.970 -s32
2.971 -ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
2.972 -{
2.973 - u32 offset;
2.974 -
2.975 - for (offset = 0; offset < hw->mac.vft_size; offset++)
2.976 - IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
2.977 -
2.978 - for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
2.979 - IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
2.980 - IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
2.981 - IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
2.982 - }
2.983 -
2.984 - return (IXGBE_SUCCESS);
2.985 -}
2.986 -
2.987 -/*
2.988 - * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
2.989 - * @hw: pointer to hardware structure
2.990 - */
2.991 -s32
2.992 -ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
2.993 -{
2.994 - int i;
2.995 - DEBUGOUT(" Clearing UTA\n");
2.996 -
2.997 - for (i = 0; i < 128; i++)
2.998 - IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2.999 -
2.1000 - return (IXGBE_SUCCESS);
2.1001 }
2.1002
2.1003 /*
2.1004 @@ -1319,6 +1010,8 @@
2.1005 int i;
2.1006 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
2.1007 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
2.1008 +
2.1009 + DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
2.1010
2.1011 /*
2.1012 * Before starting reinitialization process,
2.1013 @@ -1396,6 +1089,8 @@
2.1014 u32 fdirctrl = 0;
2.1015 u32 pbsize;
2.1016 int i;
2.1017 +
2.1018 + DEBUGFUNC("ixgbe_init_fdir_signature_82599");
2.1019
2.1020 /*
2.1021 * Before enabling Flow Director, the Rx Packet Buffer size
2.1022 @@ -1488,6 +1183,8 @@
2.1023 u32 fdirctrl = 0;
2.1024 u32 pbsize;
2.1025 int i;
2.1026 +
2.1027 + DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
2.1028
2.1029 /*
2.1030 * Before enabling Flow Director, the Rx Packet Buffer size
2.1031 @@ -1626,6 +1323,8 @@
2.1032 u16 hash_result = 0;
2.1033 int i, j, k, h;
2.1034
2.1035 + DEBUGFUNC("ixgbe_atr_compute_hash_82599");
2.1036 +
2.1037 /*
2.1038 * Initialize the fill member to prevent warnings
2.1039 * on some compilers
2.1040 @@ -1704,6 +1403,8 @@
2.1041 s32
2.1042 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
2.1043 {
2.1044 + DEBUGFUNC("ixgbe_atr_set_vlan_id_82599");
2.1045 +
2.1046 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
2.1047 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
2.1048
2.1049 @@ -1718,6 +1419,8 @@
2.1050 s32
2.1051 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
2.1052 {
2.1053 + DEBUGFUNC("ixgbe_atr_set_src_ipv4_82599");
2.1054 +
2.1055 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
2.1056 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
2.1057 (src_addr >> 16) & 0xff;
2.1058 @@ -1736,6 +1439,8 @@
2.1059 s32
2.1060 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
2.1061 {
2.1062 + DEBUGFUNC("ixgbe_atr_set_dst_ipv4_82599");
2.1063 +
2.1064 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
2.1065 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
2.1066 (dst_addr >> 16) & 0xff;
2.1067 @@ -1758,6 +1463,8 @@
2.1068 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
2.1069 u32 src_addr_1, u32 src_addr_2, u32 src_addr_3, u32 src_addr_4)
2.1070 {
2.1071 + DEBUGFUNC("ixgbe_atr_set_src_ipv6_82599");
2.1072 +
2.1073 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
2.1074 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
2.1075 (src_addr_4 >> 8) & 0xff;
2.1076 @@ -1801,6 +1508,8 @@
2.1077 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
2.1078 u32 dst_addr_1, u32 dst_addr_2, u32 dst_addr_3, u32 dst_addr_4)
2.1079 {
2.1080 + DEBUGFUNC("ixgbe_atr_set_dst_ipv6_82599");
2.1081 +
2.1082 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
2.1083 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
2.1084 (dst_addr_4 >> 8) & 0xff;
2.1085 @@ -1840,6 +1549,8 @@
2.1086 s32
2.1087 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
2.1088 {
2.1089 + DEBUGFUNC("ixgbe_atr_set_src_port_82599");
2.1090 +
2.1091 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
2.1092 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
2.1093
2.1094 @@ -1854,6 +1565,8 @@
2.1095 s32
2.1096 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
2.1097 {
2.1098 + DEBUGFUNC("ixgbe_atr_set_dst_port_82599");
2.1099 +
2.1100 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
2.1101 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
2.1102
2.1103 @@ -1868,6 +1581,8 @@
2.1104 s32
2.1105 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
2.1106 {
2.1107 + DEBUGFUNC("ixgbe_atr_set_flex_byte_82599");
2.1108 +
2.1109 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
2.1110 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
2.1111
2.1112 @@ -1882,6 +1597,8 @@
2.1113 s32
2.1114 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input, u8 vm_pool)
2.1115 {
2.1116 + DEBUGFUNC("ixgbe_atr_set_vm_pool_82599");
2.1117 +
2.1118 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
2.1119
2.1120 return (IXGBE_SUCCESS);
2.1121 @@ -1895,6 +1612,8 @@
2.1122 s32
2.1123 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
2.1124 {
2.1125 + DEBUGFUNC("ixgbe_atr_set_l4type_82599");
2.1126 +
2.1127 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
2.1128
2.1129 return (IXGBE_SUCCESS);
2.1130 @@ -1908,6 +1627,8 @@
2.1131 s32
2.1132 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan)
2.1133 {
2.1134 + DEBUGFUNC("ixgbe_atr_get_vlan_id_82599");
2.1135 +
2.1136 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
2.1137 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
2.1138
2.1139 @@ -1922,6 +1643,8 @@
2.1140 s32
2.1141 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input, u32 *src_addr)
2.1142 {
2.1143 + DEBUGFUNC("ixgbe_atr_get_src_ipv4_82599");
2.1144 +
2.1145 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
2.1146 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
2.1147 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
2.1148 @@ -1938,6 +1661,8 @@
2.1149 s32
2.1150 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 *dst_addr)
2.1151 {
2.1152 + DEBUGFUNC("ixgbe_atr_get_dst_ipv4_82599");
2.1153 +
2.1154 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
2.1155 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
2.1156 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
2.1157 @@ -1958,6 +1683,8 @@
2.1158 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
2.1159 u32 *src_addr_1, u32 *src_addr_2, u32 *src_addr_3, u32 *src_addr_4)
2.1160 {
2.1161 + DEBUGFUNC("ixgbe_atr_get_src_ipv6_82599");
2.1162 +
2.1163 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
2.1164 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
2.1165 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
2.1166 @@ -1993,6 +1720,8 @@
2.1167 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
2.1168 u32 *dst_addr_1, u32 *dst_addr_2, u32 *dst_addr_3, u32 *dst_addr_4)
2.1169 {
2.1170 + DEBUGFUNC("ixgbe_atr_get_dst_ipv6_82599");
2.1171 +
2.1172 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12];
2.1173 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8;
2.1174 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16;
2.1175 @@ -2029,6 +1758,8 @@
2.1176 s32
2.1177 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input, u16 *src_port)
2.1178 {
2.1179 + DEBUGFUNC("ixgbe_atr_get_src_port_82599");
2.1180 +
2.1181 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
2.1182 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
2.1183
2.1184 @@ -2048,6 +1779,8 @@
2.1185 s32
2.1186 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input, u16 *dst_port)
2.1187 {
2.1188 + DEBUGFUNC("ixgbe_atr_get_dst_port_82599");
2.1189 +
2.1190 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
2.1191 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
2.1192
2.1193 @@ -2062,6 +1795,8 @@
2.1194 s32
2.1195 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input, u16 *flex_byte)
2.1196 {
2.1197 + DEBUGFUNC("ixgbe_atr_get_flex_byte_82599");
2.1198 +
2.1199 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
2.1200 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
2.1201
2.1202 @@ -2076,6 +1811,8 @@
2.1203 s32
2.1204 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input, u8 *vm_pool)
2.1205 {
2.1206 + DEBUGFUNC("ixgbe_atr_get_vm_pool_82599");
2.1207 +
2.1208 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
2.1209
2.1210 return (IXGBE_SUCCESS);
2.1211 @@ -2089,6 +1826,8 @@
2.1212 s32
2.1213 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input, u8 *l4type)
2.1214 {
2.1215 + DEBUGFUNC("ixgbe_atr_get_l4type__82599");
2.1216 +
2.1217 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
2.1218
2.1219 return (IXGBE_SUCCESS);
2.1220 @@ -2109,6 +1848,8 @@
2.1221 u32 fdirhash;
2.1222 u16 bucket_hash, sig_hash;
2.1223 u8 l4type;
2.1224 +
2.1225 + DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
2.1226
2.1227 bucket_hash = ixgbe_atr_compute_hash_82599(input,
2.1228 IXGBE_ATR_BUCKET_HASH_KEY);
2.1229 @@ -2179,6 +1920,8 @@
2.1230 u16 src_port, dst_port, vlan_id, flex_bytes;
2.1231 u16 bucket_hash;
2.1232 u8 l4type;
2.1233 +
2.1234 + DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
2.1235
2.1236 /* Get our input values */
2.1237 (void) ixgbe_atr_get_l4type_82599(input, &l4type);
2.1238 @@ -2269,6 +2012,8 @@
2.1239 {
2.1240 u32 core_ctl;
2.1241
2.1242 + DEBUGFUNC("ixgbe_read_analog_reg8_82599");
2.1243 +
2.1244 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2.1245 (reg << 8));
2.1246 IXGBE_WRITE_FLUSH(hw);
2.1247 @@ -2292,6 +2037,8 @@
2.1248 {
2.1249 u32 core_ctl;
2.1250
2.1251 + DEBUGFUNC("ixgbe_write_analog_reg8_82599");
2.1252 +
2.1253 core_ctl = (reg << 8) | val;
2.1254 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2.1255 IXGBE_WRITE_FLUSH(hw);
2.1256 @@ -2311,14 +2058,16 @@
2.1257 s32
2.1258 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw)
2.1259 {
2.1260 - u32 q_num;
2.1261 + u32 i;
2.1262 s32 ret_val = IXGBE_SUCCESS;
2.1263 +
2.1264 + DEBUGFUNC("ixgbe_start_hw_rev_1__82599");
2.1265
2.1266 ret_val = ixgbe_start_hw_generic(hw);
2.1267
2.1268 /* Clear the rate limiters */
2.1269 - for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
2.1270 - IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
2.1271 + for (i = 0; i < hw->mac.max_tx_queues; i++) {
2.1272 + IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
2.1273 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
2.1274 }
2.1275 IXGBE_WRITE_FLUSH(hw);
2.1276 @@ -2344,6 +2093,8 @@
2.1277 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2.1278 {
2.1279 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2.1280 +
2.1281 + DEBUGFUNC("ixgbe_identify_phy_82599");
2.1282
2.1283 /* Detect PHY if not unknown - returns success if already detected. */
2.1284 status = ixgbe_identify_phy_generic(hw);
2.1285 @@ -2380,10 +2131,12 @@
2.1286 u16 ext_ability = 0;
2.1287 u8 comp_codes_10g = 0;
2.1288
2.1289 + DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
2.1290 +
2.1291 hw->phy.ops.identify(hw);
2.1292
2.1293 if (hw->phy.type == ixgbe_phy_tn ||
2.1294 - hw->phy.type == ixgbe_phy_tn ||
2.1295 + hw->phy.type == ixgbe_phy_aq ||
2.1296 hw->phy.type == ixgbe_phy_cu_unknown) {
2.1297 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2.1298 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
2.1299 @@ -2483,6 +2236,8 @@
2.1300 int i;
2.1301 int secrxreg;
2.1302
2.1303 + DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2.1304 +
2.1305 /*
2.1306 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2.1307 * If traffic is incoming before we enable the Rx unit, it could hang
2.1308 @@ -2526,118 +2281,11 @@
2.1309 s32
2.1310 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
2.1311 {
2.1312 + DEBUGFUNC("ixgbe_get_device_caps_82599");
2.1313 +
2.1314 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2.1315
2.1316 return (IXGBE_SUCCESS);
2.1317 -}
2.1318 -
2.1319 -/*
2.1320 - * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
2.1321 - * @hw: pointer to hardware structure
2.1322 - * @san_mac_offset: SAN MAC address offset
2.1323 - *
2.1324 - * This function will read the EEPROM location for the SAN MAC address
2.1325 - * pointer, and returns the value at that location. This is used in both
2.1326 - * get and set mac_addr routines.
2.1327 - */
2.1328 -s32
2.1329 -ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw, u16 *san_mac_offset)
2.1330 -{
2.1331 - /*
2.1332 - * First read the EEPROM pointer to see if the MAC addresses are
2.1333 - * available.
2.1334 - */
2.1335 - hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2.1336 -
2.1337 - return (IXGBE_SUCCESS);
2.1338 -}
2.1339 -
2.1340 -/*
2.1341 - * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
2.1342 - * @hw: pointer to hardware structure
2.1343 - * @san_mac_addr: SAN MAC address
2.1344 - *
2.1345 - * Reads the SAN MAC address from the EEPROM, if it's available. This is
2.1346 - * per-port, so set_lan_id() must be called before reading the addresses.
2.1347 - * set_lan_id() is called by identify_sfp(), but this cannot be relied
2.1348 - * upon for non-SFP connections, so we must call it here.
2.1349 - */
2.1350 -s32
2.1351 -ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
2.1352 -{
2.1353 - u16 san_mac_data, san_mac_offset;
2.1354 - u8 i;
2.1355 -
2.1356 - /*
2.1357 - * First read the EEPROM pointer to see if the MAC addresses are
2.1358 - * available. If they're not, no point in calling set_lan_id() here.
2.1359 - */
2.1360 - (void) ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
2.1361 -
2.1362 - if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2.1363 - /*
2.1364 - * No addresses available in this EEPROM. It's not an
2.1365 - * error though, so just wipe the local address and return.
2.1366 - */
2.1367 - for (i = 0; i < 6; i++)
2.1368 - san_mac_addr[i] = 0xFF;
2.1369 -
2.1370 - goto san_mac_addr_out;
2.1371 - }
2.1372 -
2.1373 - /* make sure we know which port we need to program */
2.1374 - hw->mac.ops.set_lan_id(hw);
2.1375 - /* apply the port offset to the address offset */
2.1376 - (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2.1377 - (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2.1378 - for (i = 0; i < 3; i++) {
2.1379 - hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2.1380 - san_mac_addr[i * 2] = (u8)(san_mac_data);
2.1381 - san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2.1382 - san_mac_offset++;
2.1383 - }
2.1384 -
2.1385 -san_mac_addr_out:
2.1386 - return (IXGBE_SUCCESS);
2.1387 -}
2.1388 -
2.1389 -/*
2.1390 - * ixgbe_set_san_mac_addr_82599 - Write the SAN MAC address to the EEPROM
2.1391 - * @hw: pointer to hardware structure
2.1392 - * @san_mac_addr: SAN MAC address
2.1393 - *
2.1394 - * Write a SAN MAC address to the EEPROM.
2.1395 - */
2.1396 -s32
2.1397 -ixgbe_set_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
2.1398 -{
2.1399 - s32 status = IXGBE_SUCCESS;
2.1400 - u16 san_mac_data, san_mac_offset;
2.1401 - u8 i;
2.1402 -
2.1403 - /* Look for SAN mac address pointer. If not defined, return */
2.1404 - (void) ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
2.1405 -
2.1406 - if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2.1407 - status = IXGBE_ERR_NO_SAN_ADDR_PTR;
2.1408 - goto san_mac_addr_out;
2.1409 - }
2.1410 -
2.1411 - /* Make sure we know which port we need to write */
2.1412 - hw->mac.ops.set_lan_id(hw);
2.1413 - /* Apply the port offset to the address offset */
2.1414 - (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2.1415 - (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2.1416 -
2.1417 - for (i = 0; i < 3; i++) {
2.1418 - san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
2.1419 - san_mac_data |= (u16)(san_mac_addr[i * 2]);
2.1420 - hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
2.1421 - san_mac_offset++;
2.1422 - }
2.1423 -
2.1424 -san_mac_addr_out:
2.1425 - return (status);
2.1426 }
2.1427
2.1428 /*
2.1429 @@ -2656,6 +2304,8 @@
2.1430 s32 status = IXGBE_ERR_EEPROM_VERSION;
2.1431 u16 fw_offset, fw_ptp_cfg_offset;
2.1432 u16 fw_version = 0;
2.1433 +
2.1434 + DEBUGFUNC("ixgbe_verify_fw_version_82599");
2.1435
2.1436 /* firmware check is only necessary for SFI devices */
2.1437 if (hw->phy.media_type != ixgbe_media_type_fiber) {
3.1 --- a/usr/src/uts/common/io/ixgbe/ixgbe_api.c Sat Nov 07 09:32:37 2009 -0800
3.2 +++ b/usr/src/uts/common/io/ixgbe/ixgbe_api.c Sun Nov 08 15:49:56 2009 +0800
3.3 @@ -26,7 +26,7 @@
3.4 * Use is subject to license terms.
3.5 */
3.6
3.7 -/* IntelVersion: 1.120 v2-9-1-1_2009-6-10_NSW1 */
3.8 +/* IntelVersion: 1.131 scm_100309_002210 */
3.9
3.10 #include "ixgbe_api.h"
3.11 #include "ixgbe_common.h"
3.12 @@ -50,6 +50,8 @@
3.13 ixgbe_init_shared_code(struct ixgbe_hw *hw)
3.14 {
3.15 s32 status;
3.16 +
3.17 + DEBUGFUNC("ixgbe_init_shared_code");
3.18
3.19 /*
3.20 * Set the mac type
3.21 @@ -92,6 +94,7 @@
3.22 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
3.23 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
3.24 case IXGBE_DEV_ID_82598AT:
3.25 + case IXGBE_DEV_ID_82598AT2:
3.26 case IXGBE_DEV_ID_82598EB_CX4:
3.27 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
3.28 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
3.29 @@ -101,10 +104,11 @@
3.30 hw->mac.type = ixgbe_mac_82598EB;
3.31 break;
3.32 case IXGBE_DEV_ID_82599_KX4:
3.33 - case IXGBE_DEV_ID_82599_KX4_SIK:
3.34 + case IXGBE_DEV_ID_82599_KX4_MEZZ:
3.35 case IXGBE_DEV_ID_82599_XAUI_LOM:
3.36 + case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
3.37 case IXGBE_DEV_ID_82599_SFP:
3.38 - case IXGBE_DEV_ID_82599_SPW:
3.39 + case IXGBE_DEV_ID_82599_SFP_EM:
3.40 case IXGBE_DEV_ID_82599_CX4:
3.41 hw->mac.type = ixgbe_mac_82599EB;
3.42 break;
3.43 @@ -251,6 +255,22 @@
3.44 {
3.45 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps,
3.46 (hw, device_caps), IXGBE_NOT_IMPLEMENTED);
3.47 +}
3.48 +
3.49 +/*
3.50 + * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM
3.51 + * @hw: pointer to hardware structure
3.52 + * @wwnn_prefix: the alternative WWNN prefix
3.53 + * @wwpn_prefix: the alternative WWPN prefix
3.54 + *
3.55 + * This function will read the EEPROM from the alternative SAN MAC address
3.56 + * block to check the support for the alternative WWNN/WWPN prefix support.
3.57 + */
3.58 +s32
3.59 +ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, u16 *wwpn_prefix)
3.60 +{
3.61 + return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix,
3.62 + (hw, wwnn_prefix, wwpn_prefix), IXGBE_NOT_IMPLEMENTED);
3.63 }
3.64
3.65 /*
3.66 @@ -460,20 +480,6 @@
3.67 }
3.68
3.69 /*
3.70 - * ixgbe_setup_link - Configure link settings
3.71 - * @hw: pointer to hardware structure
3.72 - *
3.73 - * Configures link settings based on values in the ixgbe_hw struct.
3.74 - * Restarts the link. Performs autonegotiation if needed.
3.75 - */
3.76 -s32
3.77 -ixgbe_setup_link(struct ixgbe_hw *hw)
3.78 -{
3.79 - return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw),
3.80 - IXGBE_NOT_IMPLEMENTED);
3.81 -}
3.82 -
3.83 -/*
3.84 * ixgbe_check_link - Get link and speed status
3.85 * @hw: pointer to hardware structure
3.86 *
3.87 @@ -488,18 +494,19 @@
3.88 }
3.89
3.90 /*
3.91 - * ixgbe_setup_link_speed - Set link speed
3.92 + * ixgbe_setup_link - Set link speed
3.93 * @hw: pointer to hardware structure
3.94 * @speed: new link speed
3.95 * @autoneg: true if autonegotiation enabled
3.96 *
3.97 - * Set the link speed and restarts the link.
3.98 + * Configures link settings. Restarts the link.
3.99 + * Performs autonegotiation if needed.
3.100 */
3.101 -s32 ixgbe_setup_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
3.102 +s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
3.103 bool autoneg,
3.104 bool autoneg_wait_to_complete)
3.105 {
3.106 - return ixgbe_call_func(hw, hw->mac.ops.setup_link_speed, (hw, speed,
3.107 + return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed,
3.108 autoneg, autoneg_wait_to_complete),
3.109 IXGBE_NOT_IMPLEMENTED);
3.110 }
4.1 --- a/usr/src/uts/common/io/ixgbe/ixgbe_api.h Sat Nov 07 09:32:37 2009 -0800
4.2 +++ b/usr/src/uts/common/io/ixgbe/ixgbe_api.h Sun Nov 08 15:49:56 2009 +0800
4.3 @@ -26,7 +26,7 @@
4.4 * Use is subject to license terms.
4.5 */
4.6
4.7 -/* IntelVersion: 1.74 v2-9-1-1_2009-6-10_NSW1 */
4.8 +/* IntelVersion: 1.77 scm_100309_002210 */
4.9
4.10 #ifndef _IXGBE_API_H
4.11 #define _IXGBE_API_H
4.12 @@ -60,8 +60,7 @@
4.13 ixgbe_link_speed *speed, bool *link_up);
4.14 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
4.15 bool autoneg, bool autoneg_wait_to_complete);
4.16 -s32 ixgbe_setup_link(struct ixgbe_hw *hw);
4.17 -s32 ixgbe_setup_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
4.18 +s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
4.19 bool autoneg, bool autoneg_wait_to_complete);
4.20 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4.21 bool *link_up, bool link_up_wait_to_complete);
4.22 @@ -90,6 +89,7 @@
4.23 u32 addr_count, ixgbe_mc_addr_itr func);
4.24 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
4.25 u32 mc_addr_count, ixgbe_mc_addr_itr func);
4.26 +void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr_list, u32 vmdq);
4.27 s32 ixgbe_enable_mc(struct ixgbe_hw *hw);
4.28 s32 ixgbe_disable_mc(struct ixgbe_hw *hw);
4.29 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw);
4.30 @@ -149,5 +149,7 @@
4.31 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps);
4.32 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
4.33 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
4.34 +s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4.35 + u16 *wwpn_prefix);
4.36
4.37 #endif /* _IXGBE_API_H */
5.1 --- a/usr/src/uts/common/io/ixgbe/ixgbe_common.c Sat Nov 07 09:32:37 2009 -0800
5.2 +++ b/usr/src/uts/common/io/ixgbe/ixgbe_common.c Sun Nov 08 15:49:56 2009 +0800
5.3 @@ -25,12 +25,11 @@
5.4 * Use is subject to license terms.
5.5 */
5.6
5.7 -/* IntelVersion: 1.206 v2-9-1-1_2009-6-10_NSW1 */
5.8 +/* IntelVersion: 1.218 scm_100309_002210 */
5.9
5.10 #include "ixgbe_common.h"
5.11 #include "ixgbe_api.h"
5.12
5.13 -static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
5.14 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
5.15 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
5.16 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
5.17 @@ -45,6 +44,9 @@
5.18 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
5.19
5.20 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
5.21 +static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
5.22 + u16 *san_mac_offset);
5.23 +s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan);
5.24
5.25 /*
5.26 * ixgbe_init_ops_generic - Inits function ptrs
5.27 @@ -59,11 +61,13 @@
5.28 struct ixgbe_mac_info *mac = &hw->mac;
5.29 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5.30
5.31 + DEBUGFUNC("ixgbe_init_ops_generic");
5.32 +
5.33 /* EEPROM */
5.34 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
5.35 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
5.36 if (eec & (1 << 8))
5.37 - eeprom->ops.read = &ixgbe_read_eeprom_generic;
5.38 + eeprom->ops.read = &ixgbe_read_eerd_generic;
5.39 else
5.40 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5.41 eeprom->ops.write = &ixgbe_write_eeprom_generic;
5.42 @@ -113,7 +117,6 @@
5.43 /* Link */
5.44 mac->ops.get_link_capabilities = NULL;
5.45 mac->ops.setup_link = NULL;
5.46 - mac->ops.setup_link_speed = NULL;
5.47 mac->ops.check_link = NULL;
5.48
5.49 return (IXGBE_SUCCESS);
5.50 @@ -132,6 +135,8 @@
5.51 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
5.52 {
5.53 u32 ctrl_ext;
5.54 +
5.55 + DEBUGFUNC("ixgbe_start_hw_generic");
5.56
5.57 /* Set the media type */
5.58 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
5.59 @@ -174,6 +179,8 @@
5.60 {
5.61 s32 status = IXGBE_SUCCESS;
5.62
5.63 + DEBUGFUNC("ixgbe_init_hw_generic");
5.64 +
5.65 /* Reset the hardware */
5.66 status = hw->mac.ops.reset_hw(hw);
5.67
5.68 @@ -196,6 +203,8 @@
5.69 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
5.70 {
5.71 u16 i = 0;
5.72 +
5.73 + DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
5.74
5.75 (void) IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5.76 (void) IXGBE_READ_REG(hw, IXGBE_ILLERRC);
5.77 @@ -330,6 +339,8 @@
5.78 u32 rar_low;
5.79 u16 i;
5.80
5.81 + DEBUGFUNC("ixgbe_get_mac_addr_generic");
5.82 +
5.83 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
5.84 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
5.85
5.86 @@ -353,6 +364,8 @@
5.87 {
5.88 struct ixgbe_mac_info *mac = &hw->mac;
5.89 u16 link_status;
5.90 +
5.91 + DEBUGFUNC("ixgbe_get_bus_info_generic");
5.92
5.93 hw->bus.type = ixgbe_bus_type_pci_express;
5.94
5.95 @@ -408,6 +421,8 @@
5.96 struct ixgbe_bus_info *bus = &hw->bus;
5.97 u32 reg;
5.98
5.99 + DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
5.100 +
5.101 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
5.102 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
5.103 bus->lan_id = bus->func;
5.104 @@ -433,6 +448,8 @@
5.105 u32 number_of_queues;
5.106 u32 reg_val;
5.107 u16 i;
5.108 +
5.109 + DEBUGFUNC("ixgbe_stop_adapter_generic");
5.110
5.111 /*
5.112 * Set the adapter_stopped flag so other driver functions stop touching
5.113 @@ -484,6 +501,8 @@
5.114 {
5.115 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
5.116
5.117 + DEBUGFUNC("ixgbe_led_on_generic");
5.118 +
5.119 /* To turn on the LED, set mode to ON. */
5.120 led_reg &= ~IXGBE_LED_MODE_MASK(index);
5.121 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
5.122 @@ -502,6 +521,8 @@
5.123 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
5.124 {
5.125 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
5.126 +
5.127 + DEBUGFUNC("ixgbe_led_off_generic");
5.128
5.129 /* To turn off the LED, set mode to OFF. */
5.130 led_reg &= ~IXGBE_LED_MODE_MASK(index);
5.131 @@ -526,6 +547,8 @@
5.132 u32 eec;
5.133 u16 eeprom_size;
5.134
5.135 + DEBUGFUNC("ixgbe_init_eeprom_params_generic");
5.136 +
5.137 if (eeprom->type == ixgbe_eeprom_uninitialized) {
5.138 eeprom->type = ixgbe_eeprom_none;
5.139 /*
5.140 @@ -549,7 +572,7 @@
5.141 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
5.142 IXGBE_EEC_SIZE_SHIFT);
5.143 eeprom->word_size = 1 << (eeprom_size +
5.144 - IXGBE_EEPROM_WORD_SIZE_SHIFT);
5.145 + IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT);
5.146 }
5.147
5.148 if (eec & IXGBE_EEC_ADDR_SIZE)
5.149 @@ -578,6 +601,8 @@
5.150 {
5.151 s32 status;
5.152 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
5.153 +
5.154 + DEBUGFUNC("ixgbe_write_eeprom_generic");
5.155
5.156 hw->eeprom.ops.init_params(hw);
5.157
5.158 @@ -647,6 +672,8 @@
5.159 u16 word_in;
5.160 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
5.161
5.162 + DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
5.163 +
5.164 hw->eeprom.ops.init_params(hw);
5.165
5.166 if (offset >= hw->eeprom.word_size) {
5.167 @@ -693,7 +720,7 @@
5.168 }
5.169
5.170 /*
5.171 - * ixgbe_read_eeprom_generic - Read EEPROM word using EERD
5.172 + * ixgbe_read_eerd_generic - Read EEPROM word using EERD
5.173 * @hw: pointer to hardware structure
5.174 * @offset: offset of word in the EEPROM to read
5.175 * @data: word read from the EEPROM
5.176 @@ -701,10 +728,12 @@
5.177 * Reads a 16 bit word from the EEPROM using the EERD register.
5.178 */
5.179 s32
5.180 -ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
5.181 +ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
5.182 {
5.183 u32 eerd;
5.184 s32 status;
5.185 +
5.186 + DEBUGFUNC("ixgbe_read_eerd_generic");
5.187
5.188 hw->eeprom.ops.init_params(hw);
5.189
5.190 @@ -713,39 +742,46 @@
5.191 goto out;
5.192 }
5.193
5.194 - eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) +
5.195 - IXGBE_EEPROM_READ_REG_START;
5.196 + eerd = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) +
5.197 + IXGBE_EEPROM_RW_REG_START;
5.198
5.199 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
5.200 - status = ixgbe_poll_eeprom_eerd_done(hw);
5.201 + status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
5.202
5.203 - if (status == IXGBE_SUCCESS) {
5.204 + if (status == IXGBE_SUCCESS)
5.205 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
5.206 - IXGBE_EEPROM_READ_REG_DATA);
5.207 - } else {
5.208 + IXGBE_EEPROM_RW_REG_DATA);
5.209 + else
5.210 DEBUGOUT("Eeprom read timed out\n");
5.211 - }
5.212
5.213 out:
5.214 return (status);
5.215 }
5.216
5.217 /*
5.218 - * ixgbe_poll_eeprom_eerd_done - Poll EERD status
5.219 + * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
5.220 * @hw: pointer to hardware structure
5.221 + * @ee_reg: EEPROM flag for polling
5.222 *
5.223 - * Polls the status bit (bit 1) of the EERD to determine when the read is done.
5.224 + * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
5.225 + * read or write is done respectively.
5.226 */
5.227 -static s32
5.228 -ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw)
5.229 +s32
5.230 +ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
5.231 {
5.232 u32 i;
5.233 u32 reg;
5.234 s32 status = IXGBE_ERR_EEPROM;
5.235
5.236 - for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) {
5.237 - reg = IXGBE_READ_REG(hw, IXGBE_EERD);
5.238 - if (reg & IXGBE_EEPROM_READ_REG_DONE) {
5.239 + DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
5.240 +
5.241 + for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
5.242 + if (ee_reg == IXGBE_NVM_POLL_READ)
5.243 + reg = IXGBE_READ_REG(hw, IXGBE_EERD);
5.244 + else
5.245 + reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
5.246 +
5.247 + if (reg & IXGBE_EEPROM_RW_REG_DONE) {
5.248 status = IXGBE_SUCCESS;
5.249 break;
5.250 }
5.251 @@ -767,6 +803,8 @@
5.252 s32 status = IXGBE_SUCCESS;
5.253 u32 eec;
5.254 u32 i;
5.255 +
5.256 + DEBUGFUNC("ixgbe_acquire_eeprom");
5.257
5.258 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS)
5.259 status = IXGBE_ERR_SWFW_SYNC;
5.260 @@ -820,6 +858,8 @@
5.261 u32 timeout = 2000;
5.262 u32 i;
5.263 u32 swsm;
5.264 +
5.265 + DEBUGFUNC("ixgbe_get_eeprom_semaphore");
5.266
5.267 /* Get SMBI software semaphore between device drivers first */
5.268 for (i = 0; i < timeout; i++) {
5.269 @@ -884,6 +924,8 @@
5.270 {
5.271 u32 swsm;
5.272
5.273 + DEBUGFUNC("ixgbe_release_eeprom_semaphore");
5.274 +
5.275 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
5.276
5.277 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
5.278 @@ -902,6 +944,8 @@
5.279 s32 status = IXGBE_SUCCESS;
5.280 u16 i;
5.281 u8 spi_stat_reg;
5.282 +
5.283 + DEBUGFUNC("ixgbe_ready_eeprom");
5.284
5.285 /*
5.286 * Read "Status Register" repeatedly until the LSB is cleared. The
5.287 @@ -941,6 +985,8 @@
5.288 {
5.289 u32 eec;
5.290
5.291 + DEBUGFUNC("ixgbe_standby_eeprom");
5.292 +
5.293 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5.294
5.295 /* Toggle CS to flush commands */
5.296 @@ -967,6 +1013,8 @@
5.297 u32 eec;
5.298 u32 mask;
5.299 u32 i;
5.300 +
5.301 + DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
5.302
5.303 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5.304
5.305 @@ -1021,6 +1069,8 @@
5.306 u32 i;
5.307 u16 data = 0;
5.308
5.309 + DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
5.310 +
5.311 /*
5.312 * In order to read a register from the EEPROM, we need to shift
5.313 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
5.314 @@ -1056,6 +1106,8 @@
5.315 static void
5.316 ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
5.317 {
5.318 + DEBUGFUNC("ixgbe_raise_eeprom_clk");
5.319 +
5.320 /*
5.321 * Raise the clock input to the EEPROM
5.322 * (setting the SK bit), then delay
5.323 @@ -1074,6 +1126,8 @@
5.324 static void
5.325 ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
5.326 {
5.327 + DEBUGFUNC("ixgbe_lower_eeprom_clk");
5.328 +
5.329 /*
5.330 * Lower the clock input to the EEPROM (clearing the SK bit), then
5.331 * delay
5.332 @@ -1092,6 +1146,8 @@
5.333 ixgbe_release_eeprom(struct ixgbe_hw *hw)
5.334 {
5.335 u32 eec;
5.336 +
5.337 + DEBUGFUNC("ixgbe_release_eeprom");
5.338
5.339 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5.340
5.341 @@ -1126,6 +1182,8 @@
5.342 u16 length = 0;
5.343 u16 pointer = 0;
5.344 u16 word = 0;
5.345 +
5.346 + DEBUGFUNC("ixgbe_calc_eeprom_checksum");
5.347
5.348 /* Include 0x0-0x3F in the checksum */
5.349 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
5.350 @@ -1174,6 +1232,8 @@
5.351 u16 checksum;
5.352 u16 read_checksum = 0;
5.353
5.354 + DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
5.355 +
5.356 /*
5.357 * Read the first word from the EEPROM. If this times out or fails, do
5.358 * not continue or we could be in for a very long wait while every
5.359 @@ -1213,6 +1273,8 @@
5.360 s32 status;
5.361 u16 checksum;
5.362
5.363 + DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
5.364 +
5.365 /*
5.366 * Read the first word from the EEPROM. If this times out or fails, do
5.367 * not continue or we could be in for a very long wait while every
5.368 @@ -1241,6 +1303,8 @@
5.369 ixgbe_validate_mac_addr(u8 *mac_addr)
5.370 {
5.371 s32 status = IXGBE_SUCCESS;
5.372 +
5.373 + DEBUGFUNC("ixgbe_validate_mac_addr");
5.374
5.375 /* Make sure it is not a multicast address */
5.376 if (IXGBE_IS_MULTICAST(mac_addr)) {
5.377 @@ -1275,6 +1339,8 @@
5.378 {
5.379 u32 rar_low, rar_high;
5.380 u32 rar_entries = hw->mac.num_rar_entries;
5.381 +
5.382 + DEBUGFUNC("ixgbe_set_rar_generic");
5.383
5.384 /* setup VMDq pool selection before this RAR gets enabled */
5.385 hw->mac.ops.set_vmdq(hw, index, vmdq);
5.386 @@ -1323,6 +1389,8 @@
5.387 u32 rar_high;
5.388 u32 rar_entries = hw->mac.num_rar_entries;
5.389
5.390 + DEBUGFUNC("ixgbe_clear_rar_generic");
5.391 +
5.392 /* Make sure we are using a valid rar index range */
5.393 if (index < rar_entries) {
5.394 /*
5.395 @@ -1358,6 +1426,8 @@
5.396 {
5.397 u32 i;
5.398 u32 rar_entries = hw->mac.num_rar_entries;
5.399 +
5.400 + DEBUGFUNC("ixgbe_init_rx_addrs_generic");
5.401
5.402 /*
5.403 * If the current mac address is valid, assume it is a software override
5.404 @@ -1423,6 +1493,8 @@
5.405 u32 rar_entries = hw->mac.num_rar_entries;
5.406 u32 rar;
5.407
5.408 + DEBUGFUNC("ixgbe_add_uc_addr");
5.409 +
5.410 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
5.411 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
5.412
5.413 @@ -1466,6 +1538,8 @@
5.414 u32 uc_addr_in_use;
5.415 u32 fctrl;
5.416 u32 vmdq;
5.417 +
5.418 + DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
5.419
5.420 /*
5.421 * Clear accounting of old secondary address list,
5.422 @@ -1528,6 +1602,8 @@
5.423 {
5.424 u32 vector = 0;
5.425
5.426 + DEBUGFUNC("ixgbe_mta_vector");
5.427 +
5.428 switch (hw->mac.mc_filter_type) {
5.429 case 0: /* use bits [47:36] of the address */
5.430 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
5.431 @@ -1566,6 +1642,8 @@
5.432 u32 vector_bit;
5.433 u32 vector_reg;
5.434 u32 mta_reg;
5.435 +
5.436 + DEBUGFUNC("ixgbe_set_mta");
5.437
5.438 hw->addr_ctrl.mta_in_use++;
5.439
5.440 @@ -1607,6 +1685,8 @@
5.441 u32 i;
5.442 u32 vmdq;
5.443
5.444 + DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
5.445 +
5.446 /*
5.447 * Set the new number of MC addresses that we are being requested to
5.448 * use.
5.449 @@ -1645,6 +1725,8 @@
5.450 {
5.451 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
5.452
5.453 + DEBUGFUNC("ixgbe_enable_mc_generic");
5.454 +
5.455 if (a->mta_in_use > 0)
5.456 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
5.457 hw->mac.mc_filter_type);
5.458 @@ -1662,6 +1744,8 @@
5.459 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
5.460 {
5.461 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
5.462 +
5.463 + DEBUGFUNC("ixgbe_disable_mc_generic");
5.464
5.465 if (a->mta_in_use > 0)
5.466 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5.467 @@ -1740,7 +1824,7 @@
5.468 break;
5.469 default:
5.470 DEBUGOUT("Flow control param set incorrectly\n");
5.471 - ret_val = -IXGBE_ERR_CONFIG;
5.472 + ret_val = IXGBE_ERR_CONFIG;
5.473 goto out;
5.474 }
5.475
5.476 @@ -1810,6 +1894,7 @@
5.477 s32 ret_val = IXGBE_SUCCESS;
5.478 ixgbe_link_speed speed;
5.479 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
5.480 + u32 links2, anlp1_reg, autoc_reg, links;
5.481 bool link_up;
5.482
5.483 DEBUGFUNC("ixgbe_fc_autoneg");
5.484 @@ -1818,27 +1903,61 @@
5.485 * AN should have completed when the cable was plugged in.
5.486 * Look for reasons to bail out. Bail out if:
5.487 * - FC autoneg is disabled, or if
5.488 - * - we don't have multispeed fiber, or if
5.489 - * - we're not running at 1G, or if
5.490 - * - link is not up, or if
5.491 - * - link is up but AN did not complete, or if
5.492 - * - link is up and AN completed but timed out
5.493 + * - link is not up.
5.494 *
5.495 - * Since we're being called from an LSC, link is already know to be up.
5.496 + * Since we're being called from an LSC, link is already known to be up.
5.497 * So use link_up_wait_to_complete=false.
5.498 */
5.499 hw->mac.ops.check_link(hw, &speed, &link_up, false);
5.500 - linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
5.501
5.502 - if (hw->fc.disable_fc_autoneg ||
5.503 - !hw->phy.multispeed_fiber ||
5.504 - (speed != IXGBE_LINK_SPEED_1GB_FULL) ||
5.505 - !link_up ||
5.506 - ((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
5.507 - ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
5.508 + if (hw->fc.disable_fc_autoneg || (!link_up)) {
5.509 hw->fc.fc_was_autonegged = false;
5.510 hw->fc.current_mode = hw->fc.requested_mode;
5.511 - DEBUGOUT("Autoneg FC was skipped.\n");
5.512 + goto out;
5.513 + }
5.514 +
5.515 + /*
5.516 + * On backplane, bail out if
5.517 + * - backplane autoneg was not completed, or if
5.518 + * - link partner is not AN enabled
5.519 + */
5.520 + if (hw->phy.media_type == ixgbe_media_type_backplane) {
5.521 + links = IXGBE_READ_REG(hw, IXGBE_LINKS);
5.522 + links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
5.523 + if (((links & IXGBE_LINKS_KX_AN_COMP) == 0) ||
5.524 + ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)) {
5.525 + hw->fc.fc_was_autonegged = false;
5.526 + hw->fc.current_mode = hw->fc.requested_mode;
5.527 + goto out;
5.528 + }
5.529 + }
5.530 +
5.531 + /*
5.532 + * On multispeed fiber at 1g, bail out if
5.533 + * - link is up but AN did not complete, or if
5.534 + * - link is up and AN completed but timed out
5.535 + */
5.536 + if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL)) {
5.537 + linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
5.538 + if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
5.539 + ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
5.540 + hw->fc.fc_was_autonegged = false;
5.541 + hw->fc.current_mode = hw->fc.requested_mode;
5.542 + goto out;
5.543 + }
5.544 + }
5.545 +
5.546 + /*
5.547 + * Bail out on
5.548 + * - copper or CX4 adapters
5.549 + * - fiber adapters running at 10gig
5.550 + */
5.551 + if ((hw->phy.media_type == ixgbe_media_type_copper) ||
5.552 + (hw->phy.media_type == ixgbe_media_type_cx4) ||
5.553 + ((hw->phy.media_type == ixgbe_media_type_fiber) &&
5.554 + (speed == IXGBE_LINK_SPEED_10GB_FULL))) {
5.555 + hw->fc.fc_was_autonegged = false;
5.556 + hw->fc.current_mode = hw->fc.requested_mode;
5.557 goto out;
5.558 }
5.559
5.560 @@ -1846,41 +1965,85 @@
5.561 * Read the AN advertisement and LP ability registers and resolve
5.562 * local flow control settings accordingly
5.563 */
5.564 - pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
5.565 - pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
5.566 - if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
5.567 - (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
5.568 - /*
5.569 - * Now we need to check if the user selected Rx ONLY
5.570 - * of pause frames. In this case, we had to advertise
5.571 - * FULL flow control because we could not advertise RX
5.572 - * ONLY. Hence, we must now check to see if we need to
5.573 - * turn OFF the TRANSMISSION of PAUSE frames.
5.574 - */
5.575 - if (hw->fc.requested_mode == ixgbe_fc_full) {
5.576 - hw->fc.current_mode = ixgbe_fc_full;
5.577 - DEBUGOUT("Flow Control = FULL.\n");
5.578 - } else {
5.579 + if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
5.580 + (hw->phy.media_type != ixgbe_media_type_backplane)) {
5.581 + pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
5.582 + pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
5.583 + if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
5.584 + (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
5.585 + /*
5.586 + * Now we need to check if the user selected Rx ONLY
5.587 + * of pause frames. In this case, we had to advertise
5.588 + * FULL flow control because we could not advertise RX
5.589 + * ONLY. Hence, we must now check to see if we need to
5.590 + * turn OFF the TRANSMISSION of PAUSE frames.
5.591 + */
5.592 + if (hw->fc.requested_mode == ixgbe_fc_full) {
5.593 + hw->fc.current_mode = ixgbe_fc_full;
5.594 + DEBUGOUT("Flow Control = FULL.\n");
5.595 + } else {
5.596 + hw->fc.current_mode = ixgbe_fc_rx_pause;
5.597 + DEBUGOUT("Flow Control=RX PAUSE frames only\n");
5.598 + }
5.599 + } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
5.600 + (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
5.601 + (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
5.602 + (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
5.603 + hw->fc.current_mode = ixgbe_fc_tx_pause;
5.604 + DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
5.605 + } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
5.606 + (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
5.607 + !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
5.608 + (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
5.609 hw->fc.current_mode = ixgbe_fc_rx_pause;
5.610 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
5.611 + } else {
5.612 + hw->fc.current_mode = ixgbe_fc_none;
5.613 + DEBUGOUT("Flow Control = NONE.\n");
5.614 }
5.615 - } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
5.616 - (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
5.617 - (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
5.618 - (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
5.619 - hw->fc.current_mode = ixgbe_fc_tx_pause;
5.620 - DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
5.621 - } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
5.622 - (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
5.623 - !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
5.624 - (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
5.625 - hw->fc.current_mode = ixgbe_fc_rx_pause;
5.626 - DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
5.627 - } else {
5.628 - hw->fc.current_mode = ixgbe_fc_none;
5.629 - DEBUGOUT("Flow Control = NONE.\n");
5.630 }
5.631
5.632 + if (hw->phy.media_type == ixgbe_media_type_backplane) {
5.633 + /*
5.634 + * Read the 10g AN autoc and LP ability registers and resolve
5.635 + * local flow control settings accordingly
5.636 + */
5.637 + autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
5.638 + anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
5.639 +
5.640 + if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
5.641 + (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE)) {
5.642 + /*
5.643 + * Now we need to check if the user selected Rx ONLY
5.644 + * of pause frames. In this case, we had to advertise
5.645 + * FULL flow control because we could not advertise RX
5.646 + * ONLY. Hence, we must now check to see if we need to
5.647 + * turn OFF the TRANSMISSION of PAUSE frames.
5.648 + */
5.649 + if (hw->fc.requested_mode == ixgbe_fc_full) {
5.650 + hw->fc.current_mode = ixgbe_fc_full;
5.651 + DEBUGOUT("Flow Control = FULL.\n");
5.652 + } else {
5.653 + hw->fc.current_mode = ixgbe_fc_rx_pause;
5.654 + DEBUGOUT("Flow Control=RX PAUSE frames only\n");
5.655 + }
5.656 + } else if (!(autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
5.657 + (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) &&
5.658 + (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) &&
5.659 + (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) {
5.660 + hw->fc.current_mode = ixgbe_fc_tx_pause;
5.661 + DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
5.662 + } else if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
5.663 + (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) &&
5.664 + !(anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) &&
5.665 + (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) {
5.666 + hw->fc.current_mode = ixgbe_fc_rx_pause;
5.667 + DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
5.668 + } else {
5.669 + hw->fc.current_mode = ixgbe_fc_none;
5.670 + DEBUGOUT("Flow Control = NONE.\n");
5.671 + }
5.672 + }
5.673 /* Record that current_mode is the result of a successful autoneg */
5.674 hw->fc.fc_was_autonegged = true;
5.675
5.676 @@ -1899,6 +2062,8 @@
5.677 {
5.678 s32 ret_val = IXGBE_SUCCESS;
5.679 u32 reg;
5.680 +
5.681 + DEBUGFUNC("ixgbe_setup_fc");
5.682
5.683 /* Validate the packetbuf configuration */
5.684 if (packetbuf_num < 0 || packetbuf_num > 7) {
5.685 @@ -1982,15 +2147,12 @@
5.686 break;
5.687 default:
5.688 DEBUGOUT("Flow control param set incorrectly\n");
5.689 - ret_val = -IXGBE_ERR_CONFIG;
5.690 + ret_val = IXGBE_ERR_CONFIG;
5.691 goto out;
5.692 }
5.693
5.694 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
5.695 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
5.696 -
5.697 - /* Enable and restart autoneg to inform the link partner */
5.698 - reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART;
5.699
5.700 /* Disable AN timeout */
5.701 if (hw->fc.strict_ieee)
5.702 @@ -1998,6 +2160,64 @@
5.703
5.704 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
5.705 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
5.706 +
5.707 + /*
5.708 + * Set up the 10G flow control advertisement registers so the HW
5.709 + * can do fc autoneg once the cable is plugged in. If we end up
5.710 + * using 1g instead, this is harmless.
5.711 + */
5.712 + reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
5.713 +
5.714 + /*
5.715 + * The possible values of fc.requested_mode are:
5.716 + * 0: Flow control is completely disabled
5.717 + * 1: Rx flow control is enabled (we can receive pause frames,
5.718 + * but not send pause frames).
5.719 + * 2: Tx flow control is enabled (we can send pause frames but
5.720 + * we do not support receiving pause frames).
5.721 + * 3: Both Rx and Tx flow control (symmetric) are enabled.
5.722 + * other: Invalid.
5.723 + */
5.724 + switch (hw->fc.requested_mode) {
5.725 + case ixgbe_fc_none:
5.726 + /* Flow control completely disabled by software override. */
5.727 + reg &= ~(IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
5.728 + break;
5.729 + case ixgbe_fc_rx_pause:
5.730 + /*
5.731 + * Rx Flow control is enabled and Tx Flow control is
5.732 + * disabled by software override. Since there really
5.733 + * isn't a way to advertise that we are capable of RX
5.734 + * Pause ONLY, we will advertise that we support both
5.735 + * symmetric and asymmetric Rx PAUSE. Later, we will
5.736 + * disable the adapter's ability to send PAUSE frames.
5.737 + */
5.738 + reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
5.739 + break;
5.740 + case ixgbe_fc_tx_pause:
5.741 + /*
5.742 + * Tx Flow control is enabled, and Rx Flow control is
5.743 + * disabled by software override.
5.744 + */
5.745 + reg |= (IXGBE_AUTOC_ASM_PAUSE);
5.746 + reg &= ~(IXGBE_AUTOC_SYM_PAUSE);
5.747 + break;
5.748 + case ixgbe_fc_full:
5.749 + /* Flow control (both Rx and Tx) is enabled by SW override. */
5.750 + reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
5.751 + break;
5.752 + default:
5.753 + DEBUGOUT("Flow control param set incorrectly\n");
5.754 + ret_val = IXGBE_ERR_CONFIG;
5.755 + goto out;
5.756 + }
5.757 + /*
5.758 + * AUTOC restart handles negotiation of 1G and 10G. There is
5.759 + * no need to set the PCS1GCTL register.
5.760 + */
5.761 + reg |= IXGBE_AUTOC_AN_RESTART;
5.762 + IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg);
5.763 + DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
5.764
5.765 out:
5.766 return (ret_val);
5.767 @@ -2019,6 +2239,8 @@
5.768 u32 reg_val;
5.769 u32 number_of_queues;
5.770 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
5.771 +
5.772 + DEBUGFUNC("ixgbe_disable_pcie_master");
5.773
5.774 /* Disable the receive unit by stopping each queue */
5.775 number_of_queues = hw->mac.max_rx_queues;
5.776 @@ -2061,13 +2283,15 @@
5.777 u32 fwmask = mask << 5;
5.778 s32 timeout = 200;
5.779
5.780 + DEBUGFUNC("ixgbe_acquire_swfw_sync");
5.781 +
5.782 while (timeout) {
5.783 /*
5.784 * SW EEPROM semaphore bit is used for access to all
5.785 * SW_FW_SYNC/GSSR bits (not just EEPROM)
5.786 */
5.787 if (ixgbe_get_eeprom_semaphore(hw))
5.788 - return (-IXGBE_ERR_SWFW_SYNC);
5.789 + return (IXGBE_ERR_SWFW_SYNC);
5.790
5.791 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
5.792 if (!(gssr & (fwmask | swmask)))
5.793 @@ -2084,7 +2308,7 @@
5.794
5.795 if (!timeout) {
5.796 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
5.797 - return (-IXGBE_ERR_SWFW_SYNC);
5.798 + return (IXGBE_ERR_SWFW_SYNC);
5.799 }
5.800
5.801 gssr |= swmask;
5.802 @@ -2108,6 +2332,8 @@
5.803 u32 gssr;
5.804 u32 swmask = mask;
5.805
5.806 + DEBUGFUNC("ixgbe_release_swfw_sync");
5.807 +
5.808 (void) ixgbe_get_eeprom_semaphore(hw);
5.809
5.810 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
5.811 @@ -2127,6 +2353,8 @@
5.812 s32
5.813 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
5.814 {
5.815 + DEBUGFUNC("ixgbe_enable_rx_dma_generic");
5.816 +
5.817 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
5.818
5.819 return (IXGBE_SUCCESS);
5.820 @@ -2144,6 +2372,8 @@
5.821 bool link_up = 0;
5.822 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
5.823 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
5.824 +
5.825 + DEBUGFUNC("ixgbe_blink_led_start_generic");
5.826
5.827 /*
5.828 * Link must be up to auto-blink the LEDs;
5.829 @@ -2177,6 +2407,8 @@
5.830 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
5.831 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
5.832
5.833 + DEBUGFUNC("ixgbe_blink_led_stop_generic");
5.834 +
5.835 autoc_reg &= ~IXGBE_AUTOC_FLU;
5.836 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
5.837 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
5.838 @@ -2189,3 +2421,598 @@
5.839
5.840 return (IXGBE_SUCCESS);
5.841 }
5.842 +
5.843 +/*
5.844 + * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
5.845 + * @hw: pointer to hardware structure
5.846 + * @san_mac_offset: SAN MAC address offset
5.847 + *
5.848 + * This function will read the EEPROM location for the SAN MAC address
5.849 + * pointer, and returns the value at that location. This is used in both
5.850 + * get and set mac_addr routines.
5.851 + */
5.852 +static s32
5.853 +ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, u16 *san_mac_offset)
5.854 +{
5.855 + DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
5.856 +
5.857 + /*
5.858 + * First read the EEPROM pointer to see if the MAC addresses are
5.859 + * available.
5.860 + */
5.861 + hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
5.862 +
5.863 + return (IXGBE_SUCCESS);
5.864 +}
5.865 +
5.866 +/*
5.867 + * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
5.868 + * @hw: pointer to hardware structure
5.869 + * @san_mac_addr: SAN MAC address
5.870 + *
5.871 + * Reads the SAN MAC address from the EEPROM, if it's available. This is
5.872 + * per-port, so set_lan_id() must be called before reading the addresses.
5.873 + * set_lan_id() is called by identify_sfp(), but this cannot be relied
5.874 + * upon for non-SFP connections, so we must call it here.
5.875 + */
5.876 +s32
5.877 +ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
5.878 +{
5.879 + u16 san_mac_data, san_mac_offset;
5.880 + u8 i;
5.881 +
5.882 + DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
5.883 +
5.884 + /*
5.885 + * First read the EEPROM pointer to see if the MAC addresses are
5.886 + * available. If they're not, no point in calling set_lan_id() here.
5.887 + */
5.888 + (void) ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
5.889 +
5.890 + if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
5.891 + /*
5.892 + * No addresses available in this EEPROM. It's not an
5.893 + * error though, so just wipe the local address and return.
5.894 + */
5.895 + for (i = 0; i < 6; i++)
5.896 + san_mac_addr[i] = 0xFF;
5.897 +
5.898 + goto san_mac_addr_out;
5.899 + }
5.900 +
5.901 + /* make sure we know which port we need to program */
5.902 + hw->mac.ops.set_lan_id(hw);
5.903 + /* apply the port offset to the address offset */
5.904 + (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
5.905 + (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
5.906 + for (i = 0; i < 3; i++) {
5.907 + hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
5.908 + san_mac_addr[i * 2] = (u8)(san_mac_data);
5.909 + san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
5.910 + san_mac_offset++;
5.911 + }
5.912 +
5.913 +san_mac_addr_out:
5.914 + return (IXGBE_SUCCESS);
5.915 +}
5.916 +
5.917 +/*
5.918 + * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
5.919 + * @hw: pointer to hardware structure
5.920 + * @san_mac_addr: SAN MAC address
5.921 + *
5.922 + * Write a SAN MAC address to the EEPROM.
5.923 + */
5.924 +s32
5.925 +ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
5.926 +{
5.927 + s32 status = IXGBE_SUCCESS;
5.928 + u16 san_mac_data, san_mac_offset;
5.929 + u8 i;
5.930 +
5.931 + DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
5.932 +
5.933 + /* Look for SAN mac address pointer. If not defined, return */
5.934 + (void) ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
5.935 +
5.936 + if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
5.937 + status = IXGBE_ERR_NO_SAN_ADDR_PTR;
5.938 + goto san_mac_addr_out;
5.939 + }
5.940 +
5.941 + /* Make sure we know which port we need to write */
5.942 + hw->mac.ops.set_lan_id(hw);
5.943 + /* Apply the port offset to the address offset */
5.944 + (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
5.945 + (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
5.946 +
5.947 + for (i = 0; i < 3; i++) {
5.948 + san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
5.949 + san_mac_data |= (u16)(san_mac_addr[i * 2]);
5.950 + hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
5.951 + san_mac_offset++;
5.952 + }
5.953 +
5.954 +san_mac_addr_out:
5.955 + return (status);
5.956 +}
5.957 +
5.958 +/*
5.959 + * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
5.960 + * @hw: pointer to hardware structure
5.961 + *
5.962 + * Read PCIe configuration space, and get the MSI-X vector count from
5.963 + * the capabilities table.
5.964 + */
5.965 +u32
5.966 +ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
5.967 +{
5.968 + u32 msix_count = 64;
5.969 +
5.970 + DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
5.971 + if (hw->mac.msix_vectors_from_pcie) {
5.972 + msix_count = IXGBE_READ_PCIE_WORD(hw,
5.973 + IXGBE_PCIE_MSIX_82599_CAPS);
5.974 + msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
5.975 +
5.976 + /*
5.977 + * MSI-X count is zero-based in HW, so increment to give
5.978 + * proper value.
5.979 + */
5.980 + msix_count++;
5.981 + }
5.982 +
5.983 + return (msix_count);
5.984 +}
5.985 +
5.986 +/*
5.987 + * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
5.988 + * @hw: pointer to hardware structure
5.989 + * @addr: Address to put into receive address register
5.990 + * @vmdq: VMDq pool to assign
5.991 + *
5.992 + * Puts an ethernet address into a receive address register, or
5.993 + * finds the rar that it is aleady in; adds to the pool list
5.994 + */
5.995 +s32
5.996 +ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
5.997 +{
5.998 + static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
5.999 + u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
5.1000 + u32 rar;
5.1001 + u32 rar_low, rar_high;
5.1002 + u32 addr_low, addr_high;
5.1003 +
5.1004 + DEBUGFUNC("ixgbe_insert_mac_addr_generic");
5.1005 +
5.1006 + /* swap bytes for HW little endian */
5.1007 + addr_low = addr[0] | (addr[1] << 8)
5.1008 + | (addr[2] << 16)
5.1009 + | (addr[3] << 24);
5.1010 + addr_high = addr[4] | (addr[5] << 8);
5.1011 +
5.1012 + /*
5.1013 + * Either find the mac_id in rar or find the first empty space.
5.1014 + * rar_highwater points to just after the highest currently used
5.1015 + * rar in order to shorten the search. It grows when we add a new
5.1016 + * rar to the top.
5.1017 + */
5.1018 + for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
5.1019 + rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
5.1020 +
5.1021 + if (((IXGBE_RAH_AV & rar_high) == 0) &&
5.1022 + first_empty_rar == NO_EMPTY_RAR_FOUND) {
5.1023 + first_empty_rar = rar;
5.1024 + } else if ((rar_high & 0xFFFF) == addr_high) {
5.1025 + rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
5.1026 + if (rar_low == addr_low)
5.1027 + break; /* found it already in the rars */
5.1028 + }
5.1029 + }
5.1030 +
5.1031 + if (rar < hw->mac.rar_highwater) {
5.1032 + /* already there so just add to the pool bits */
5.1033 + (void) ixgbe_set_vmdq(hw, rar, vmdq);
5.1034 + } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
5.1035 + /* stick it into first empty RAR slot we found */
5.1036 + rar = first_empty_rar;
5.1037 + (void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
5.1038 + } else if (rar == hw->mac.rar_highwater) {
5.1039 + /* add it to the top of the list and inc the highwater mark */
5.1040 + (void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
5.1041 + hw->mac.rar_highwater++;
5.1042 + } else if (rar >= hw->mac.num_rar_entries) {
5.1043 + return (IXGBE_ERR_INVALID_MAC_ADDR);
5.1044 + }
5.1045 +
5.1046 + /*
5.1047 + * If we found rar[0], make sure the default pool bit (we use pool 0)
5.1048 + * remains cleared to be sure default pool packets will get delivered
5.1049 + */
5.1050 + if (rar == 0)
5.1051 + (void) ixgbe_clear_vmdq(hw, rar, 0);
5.1052 +
5.1053 + return (rar);
5.1054 +}
5.1055 +
5.1056 +/*
5.1057 + * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
5.1058 + * @hw: pointer to hardware struct
5.1059 + * @rar: receive address register index to disassociate
5.1060 + * @vmdq: VMDq pool index to remove from the rar
5.1061 + */
5.1062 +s32
5.1063 +ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
5.1064 +{
5.1065 + u32 mpsar_lo, mpsar_hi;
5.1066 + u32 rar_entries = hw->mac.num_rar_entries;
5.1067 +
5.1068 + DEBUGFUNC("ixgbe_clear_vmdq_generic");
5.1069 +
5.1070 + if (rar < rar_entries) {
5.1071 + mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
5.1072 + mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
5.1073 +
5.1074 + if (!mpsar_lo && !mpsar_hi)
5.1075 + goto done;
5.1076 +
5.1077 + if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
5.1078 + if (mpsar_lo) {
5.1079 + IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
5.1080 + mpsar_lo = 0;
5.1081 + }
5.1082 + if (mpsar_hi) {
5.1083 + IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
5.1084 + mpsar_hi = 0;
5.1085 + }
5.1086 + } else if (vmdq < 32) {
5.1087 + mpsar_lo &= ~(1 << vmdq);
5.1088 + IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
5.1089 + } else {
5.1090 + mpsar_hi &= ~(1 << (vmdq - 32));
5.1091 + IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
5.1092 + }
5.1093 +
5.1094 + /* was that the last pool using this rar? */
5.1095 + if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
5.1096 + hw->mac.ops.clear_rar(hw, rar);
5.1097 + } else {
5.1098 + DEBUGOUT1("RAR index %d is out of range.\n", rar);
5.1099 + }
5.1100 +
5.1101 +done:
5.1102 + return (IXGBE_SUCCESS);
5.1103 +}
5.1104 +
5.1105 +/*
5.1106 + * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
5.1107 + * @hw: pointer to hardware struct
5.1108 + * @rar: receive address register index to associate with a VMDq index
5.1109 + * @vmdq: VMDq pool index
5.1110 + */
5.1111 +s32
5.1112 +ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
5.1113 +{
5.1114 + u32 mpsar;
5.1115 + u32 rar_entries = hw->mac.num_rar_entries;
5.1116 +
5.1117 + DEBUGFUNC("ixgbe_set_vmdq_generic");
5.1118 +
5.1119 + if (rar < rar_entries) {
5.1120 + if (vmdq < 32) {
5.1121 + mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
5.1122 + mpsar |= 1 << vmdq;
5.1123 + IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
5.1124 + } else {
5.1125 + mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
5.1126 + mpsar |= 1 << (vmdq - 32);
5.1127 + IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
5.1128 + }
5.1129 + } else {
5.1130 + DEBUGOUT1("RAR index %d is out of range.\n", rar);
5.1131 + }
5.1132 + return (IXGBE_SUCCESS);
5.1133 +}
5.1134 +
5.1135 +/*
5.1136 + * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
5.1137 + * @hw: pointer to hardware structure
5.1138 + */
5.1139 +s32
5.1140 +ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
5.1141 +{
5.1142 + int i;
5.1143 +
5.1144 + DEBUGFUNC("ixgbe_init_uta_tables_generic");
5.1145 + DEBUGOUT(" Clearing UTA\n");
5.1146 +
5.1147 + for (i = 0; i < 128; i++)
5.1148 + IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5.1149 +
5.1150 + return (IXGBE_SUCCESS);
5.1151 +}
5.1152 +
5.1153 +/*
5.1154 + * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
5.1155 + * @hw: pointer to hardware structure
5.1156 + * @vlan: VLAN id to write to VLAN filter
5.1157 + *
5.1158 + * return the VLVF index where this VLAN id should be placed
5.1159 + *
5.1160 + */
5.1161 +s32
5.1162 +ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
5.1163 +{
5.1164 + u32 bits = 0;
5.1165 + u32 first_empty_slot = 0;
5.1166 + s32 regindex;
5.1167 +
5.1168 + /*
5.1169 + * Search for the vlan id in the VLVF entries. Save off the first empty
5.1170 + * slot found along the way
5.1171 + */
5.1172 + for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
5.1173 + bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
5.1174 + if (!bits && !(first_empty_slot))
5.1175 + first_empty_slot = regindex;
5.1176 + else if ((bits & 0x0FFF) == vlan)
5.1177 + break;
5.1178 + }
5.1179 +
5.1180 + /*
5.1181 + * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
5.1182 + * in the VLVF. Else use the first empty VLVF register for this
5.1183 + * vlan id.
5.1184 + */
5.1185 + if (regindex >= IXGBE_VLVF_ENTRIES) {
5.1186 + if (first_empty_slot)
5.1187 + regindex = first_empty_slot;
5.1188 + else {
5.1189 + DEBUGOUT("No space in VLVF.\n");
5.1190 + regindex = -1;
5.1191 + }
5.1192 + }
5.1193 +
5.1194 + return (regindex);
5.1195 +}
5.1196 +
5.1197 +/*
5.1198 + * ixgbe_set_vfta_generic - Set VLAN filter table
5.1199 + * @hw: pointer to hardware structure
5.1200 + * @vlan: VLAN id to write to VLAN filter
5.1201 + * @vind: VMDq output index that maps queue to VLAN id in VFVFB
5.1202 + * @vlan_on: boolean flag to turn on/off VLAN in VFVF
5.1203 + *
5.1204 + * Turn on/off specified VLAN in the VLAN filter table.
5.1205 + */
5.1206 +s32
5.1207 +ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
5.1208 +{
5.1209 + s32 regindex;
5.1210 + u32 bitindex;
5.1211 + u32 bits;
5.1212 + u32 vt;
5.1213 +
5.1214 + DEBUGFUNC("ixgbe_set_vfta_generic");
5.1215 +
5.1216 + if (vlan > 4095)
5.1217 + return (IXGBE_ERR_PARAM);
5.1218 +
5.1219 + /*
5.1220 + * this is a 2 part operation - first the VFTA, then the
5.1221 + * VLVF and VLVFB if VT Mode is set
5.1222 + */
5.1223 +
5.1224 + /*
5.1225 + * Part 1
5.1226 + * The VFTA is a bitstring made up of 128 32-bit registers
5.1227 + * that enable the particular VLAN id, much like the MTA:
5.1228 + * bits[11-5]: which register
5.1229 + * bits[4-0]: which bit in the register
5.1230 + */
5.1231 + regindex = (vlan >> 5) & 0x7F;
5.1232 + bitindex = vlan & 0x1F;
5.1233 + bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
5.1234 + if (vlan_on)
5.1235 + bits |= (1 << bitindex);
5.1236 + else
5.1237 + bits &= ~(1 << bitindex);
5.1238 + IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
5.1239 +
5.1240 +
5.1241 + /*
5.1242 + * Part 2
5.1243 + * If VT Mode is set
5.1244 + * Either vlan_on
5.1245 + * make sure the vlan is in VLVF
5.1246 + * set the vind bit in the matching VLVFB
5.1247 + * Or !vlan_on
5.1248 + * clear the pool bit and possibly the vind
5.1249 + */
5.1250 + vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5.1251 + if (vt & IXGBE_VT_CTL_VT_ENABLE) {
5.1252 + if (vlan == 0) {
5.1253 + regindex = 0;
5.1254 + } else {
5.1255 + regindex = ixgbe_find_vlvf_slot(hw, vlan);
5.1256 + if (regindex < 0)
5.1257 + goto out;
5.1258 + }
5.1259 +
5.1260 + if (vlan_on) {
5.1261 + /* set the pool bit */
5.1262 + if (vind < 32) {
5.1263 + bits = IXGBE_READ_REG(hw,
5.1